llvm-svn: 21296

  register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295

now gone.  Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.

llvm-svn: 21294

  where it is safe to do so.

llvm-svn: 21293

llvm-svn: 21292

Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
  always produces zero or one.

llvm-svn: 21291

llvm-svn: 21289

llvm-svn: 21288

with != 0 comparisons vanishing.

llvm-svn: 21287

llvm-svn: 21286

llvm-svn: 21285

llvm-svn: 21284

llvm-svn: 21283

* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)

llvm-svn: 21282

llvm-svn: 21281

Note that this probably only works for little endian targets, but is enough
to get siod working :)

llvm-svn: 21280

  0x00000..00FFF..FF
      ^      ^
      ^      ^
    any number of
    0's followed by
    some number of
    1's

    then we use dep.z to just paste zeros over the input. For the special
    cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
    because we're all about readability!!!
    that's what it's about!! readability!

  *twitch* ;D

llvm-svn: 21279

llvm-svn: 21277

llvm-svn: 21276

llvm-svn: 21275

Olden/mst, Ptrdist/bc, Obsequi, etc.

llvm-svn: 21274

llvm-svn: 21273

llvm-svn: 21272

llvm-svn: 21271

like this:

        ldah $1,1($31)
        lda $1,-1($1)
        and $0,$1,$24

instead of this:

        zap $0,252,$24

To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.

llvm-svn: 21270

things like this:

       mov r9 = 65535;;
       and r8 = r8, r9;;

To be emitted instead of:

        zxt2 r8 = r8;;

To get this back, the selector for ISD::AND should recognize this case.

llvm-svn: 21269

andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.

llvm-svn: 21268

llvm-svn: 21267

SelectionDAG to do the job with AND.  Don't legalize Z_E_I anymore as
it is gone

llvm-svn: 21266

instead.  OVerall, this increases the amount of folding we can do.

llvm-svn: 21265

ZERO_EXTEND_INREG was.

llvm-svn: 21264

llvm-svn: 21263

llvm-svn: 21262

Make llvm undef values generate ISD::UNDEF nodes

llvm-svn: 21261

Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm

llvm-svn: 21260

llvm-svn: 21258

llvm-svn: 21255

llvm-svn: 21254

llvm-svn: 21253

to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.

FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:

out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127

and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)

llvm-svn: 21252