Add an !eq() operator to TableGen.  It operates on strings only.
Use !cast<string>() to compare other types of objects.

llvm-svn: 92754

llvm-svn: 89729

llvm-svn: 89582

llvm-svn: 89566

llvm-svn: 89565

direct inclusion edge from System to Support.

llvm-svn: 85086

llvm-svn: 82244

 - This manifested as non-determinism in the .inc output in rare cases (when two
   distinct patterns ended up being equivalent, which is rather rare). That
   meant the pattern matching was non-deterministic, which could eventually mean
   the code generator selected different instructions based on the arch.

 - It's probably worth making the DAGISel ensure a total ordering (or force the
   user to), but the simple fix here is to totally order the Record* maps based
   on a unique ID.

 - PR4672, PR4711.

Yay:
--
ddunbar@giles:~$ cat ~/llvm.obj.64/lib/Target/*/*.inc | shasum
d1099ff34b21459a5a3e7021c225c080e6017ece  -
ddunbar@giles:~$ cat ~/llvm.obj.ppc/lib/Target/*/*.inc | shasum
d1099ff34b21459a5a3e7021c225c080e6017ece  -
--

llvm-svn: 79846

llvm-svn: 78848

 - Sorry, I can't help myself.

 - No intended functionality change.

llvm-svn: 74742

Implement !cast<string>.

llvm-svn: 74444

llvm-svn: 73843

llvm-svn: 73842

Revert 73074 and 73099 because Windows doesn't have POSIX
regular expressions.  We will add an OpenBSD implementation
and re-apply ASAP.

llvm-svn: 73138

Add a !patsubst operator.  Use on string types.

llvm-svn: 73099

Make IntInits and ListInits typed.  This helps deduce types of !if and
other operators.  For the rare cases where a list type cannot be
deduced, provide a []<type> syntax, where <type> is the list element
type.

llvm-svn: 73078

Add a !regmatch operator to do pattern matching in TableGen.

llvm-svn: 73074

Also fix up some 80col violations while I'm there.

llvm-svn: 71833

Implement !if, analogous to $(if) in GNU make.

llvm-svn: 71815

Graduate LLVM to the big leagues by embedding a LISP processor into TableGen.

Ok, not really, but do support some common LISP functions:

* car
* cdr
* null

llvm-svn: 71805

Implement a !foreach operator analogous to GNU make's $(foreach).
Use it on dags and lists like this:

class decls {
  string name;
}

def Decls : decls;

class B<list<string> names> : A<!foreach(Decls.name, names, !strconcat(Decls.name, ", Sr."))>;

llvm-svn: 71803

Implement a !subst operation simmilar to $(subst) in GNU make to do
def/var/string substitution on generic pattern templates.  For example:

def Type;
def v4f32 : Type;
def TYPE : Type;

class GenType<Type t> {
  let type = !(subst TYPE, v4f32, t);
}

def TheType : GenType<TYPE>;

llvm-svn: 71801

Implement !cast.

llvm-svn: 71794

Operation Enhancements

Create an OpInit class to serve as a base for all operation Inits.

Move parsing of operation constructs to separate functions and reference
from multiple places.

Add some commented out new operations.  Coming soon.

llvm-svn: 71789

of "class", so that it matches the subsequent definition.

llvm-svn: 70498

Fix multiclass inheritance to limit value resolution to new defs added
by base multiclasses.  Do not attempt to alter defs from previous base
multiclasses.  This fixes multiple multiclass inheritance.

llvm-svn: 69974

Make BinOps typed and require a type specifier for !nameconcat.  This
allows binops to be used in typed contexts such as when passing
arguments to classes.

llvm-svn: 69921

Implement !nameconcat to concatenate strings and look up the resulting
name in the symbol table, returning an object.

llvm-svn: 69822

in selectiondag patterns.  This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.

llvm-svn: 67286

llvm-svn: 66970

errors when thrown.  This gets us nice errors like this from tblgen:

CMOVL32rr: 	(set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2))
/Users/sabre/llvm/Debug/bin/tblgen: error:
Included from X86.td:116:
Parsing X86InstrInfo.td:922: In CMOVL32rr: X86cmov node requires exactly 4 operands!
def CMOVL32rr : I<0x4C, MRMSrcReg,       // if <s, GR32 = GR32
^

instead of just:

CMOVL32rr: 	(set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2))
/Users/sabre/llvm/Debug/bin/tblgen: In CMOVL32rr: X86cmov node requires exactly 4 operands!

This is all I plan to do with this, but it should be easy enough to improve if anyone 
cares (e.g. keeping more loc info in "dag" expr records in tblgen.

llvm-svn: 66898

llvm-svn: 66897

-Bring in int64_t for TableGen/Record.h and TableGen/TGLexer.h
-Define strtoull

llvm-svn: 57970

use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.

llvm-svn: 57663

by its first field, but TableGen doesn't actually enforce creating it that 
way. TableGen sorts the records that will be used to create it by the names 
of the records, not the Name field of those records.

This patch corrects the sort to use the "Name" field of the record as the 
sort key.

llvm-svn: 56106

orders, part of PR2590

llvm-svn: 55359

llvm-svn: 53179

llvm-svn: 48801

llvm-svn: 46250

llvm-svn: 46223