It was mistakenly looking at the pointer type when checking for the size of
global variables.  This is a partial fix for Radar 8673120.

llvm-svn: 119563

in the MC lowering process.

llvm-svn: 119559

Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free.

llvm-svn: 119558

llvm-svn: 119555

llvm-svn: 119551

and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368

llvm-svn: 119548

llvm-svn: 119547

llvm-svn: 119546

llvm-svn: 119539

llvm-svn: 119529

llvm-svn: 119492

llvm-svn: 119484

llvm-svn: 119462

should get the submode from the load/store multiple instruction's opcode.

llvm-svn: 119461

instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460

"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.

llvm-svn: 119435

llvm-svn: 119403

llvm-svn: 119354

llvm-svn: 119325

- Add encodings to the *LDMIA_RET instrs. Probably not needed...

llvm-svn: 119323

llvm-svn: 119321

'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310

llvm-svn: 119295

llvm-svn: 119187

iterator, not TII->OptimizeCompareInstr.

llvm-svn: 119186

llvm-svn: 119185

pass in the first place and was masked by earlier failures not warning
and aborting the block.

llvm-svn: 119184

llvm-svn: 119180

llvm-svn: 119176

llvm-svn: 119170

llvm-svn: 119167

llvm-svn: 119164

Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120

llvm-svn: 119109

llvm-svn: 119102

llvm-svn: 119098

First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place

llvm-svn: 119097

llvm-svn: 119075

llvm-svn: 119071

a single function instead of a class.  It doesn't need the
complexity that X86 does.

llvm-svn: 119070