llvm-svn: 35616

_test3:
        leaq (,%rdi,4), %rax
        orq %rdi, %rax
        ret

instead of:
_test2:
        movq %rdi, %rax
        shlq $2, %rax
        orq %rdi, %rax
        ret

llvm-svn: 35434

system assembler not groking legal instructions like "leal (,%esi,8), %ecx".

llvm-svn: 35393

1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204

moves, loads, etc. are recognized.

llvm-svn: 35031

llvm-svn: 33537

convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's.

llvm-svn: 32097

of opcode and number of operands.

llvm-svn: 31947

llvm-svn: 31794

llvm-svn: 31765

llvm-svn: 31712

llvm-svn: 31298

llvm-svn: 31262

llvm-svn: 31099

llvm-svn: 31097

llvm-svn: 31095

llvm-svn: 31093

llvm-svn: 31074

llvm-svn: 31065

llvm-svn: 31024

llvm-svn: 30938

llvm-svn: 30663

llvm-svn: 30177

actually *removes* one of the operands, instead of just assigning both operands
the same register.  This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.

llvm-svn: 30108

llvm-svn: 29275

llvm-svn: 28577

only transform a shufps to pshufd when the first two operands are the same.

llvm-svn: 28575

llvm-svn: 28574

llvm-svn: 28573

llvm-svn: 28565

currently...

llvm-svn: 28393

llvm-svn: 28223

movw. That is we promote the destination operand to r16. So
        %CH = TRUNC_R16_R8 %BP
is emitted as
        movw %bp, %cx.

This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
        movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.

We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.

Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.

llvm-svn: 28164

to optimize cases where it has to spill a lot

llvm-svn: 27801

- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377

llvm-svn: 27091

- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.

llvm-svn: 26919

   proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

llvm-svn: 26241

llvm-svn: 25915

Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place.  Other methods should also be moved if anyoneis interested. :)

llvm-svn: 25913