llvm-svn: 26478

into types.

llvm-svn: 26477

PR709, and paving the way for future progress.

llvm-svn: 26476

llvm-svn: 26475

PR709, and paving the way for future progress.

Significantly refactor autoupgrading code, to handle the more complex case
(where we upgrade one argument in a function), and fix some bugs in it.

Testcase here: llvm/test/Regression/Bytecode/memcpy.ll

llvm-svn: 26474

llvm-svn: 26473

llvm-svn: 26472

llvm-svn: 26471

  a predecessor appearing more than once in the operand list was counted as
  multiple predecessor; priority1 should be updated during scheduling;
  CycleBound was updated after the node is inserted into priority queue; one
  of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
  operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
  predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
        .text
        .align  4
        .globl  _f
_f:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        movl %eax, %edx
        imull %ecx, %edx
        imull %eax, %eax
        imull %ecx, %ecx
        addl %eax, %ecx
        leal (%ecx,%edx,2), %eax
        ret

  It is also a slight performance win (1% - 3%) for most tests.

llvm-svn: 26470

pointed out: realize the AND can provide factors and look through Casts.

llvm-svn: 26469

llvm-svn: 26468

pointing this out.

llvm-svn: 26467

llvm-svn: 26466

llvm-svn: 26465

span multiple lines.

llvm-svn: 26463

llvm-svn: 26462

multi-line comments.

llvm-svn: 26461

in the dag combiner on 176.gcc on x86.

llvm-svn: 26459

llvm-svn: 26458

llvm-svn: 26457

llvm-svn: 26456

debug forms.

llvm-svn: 26455

llvm-svn: 26454

llvm-svn: 26453

llvm-svn: 26452

llvm-svn: 26451

llvm-svn: 26450

llvm-svn: 26449

llvm-svn: 26448

void foo(float a, int *b) { *b = a; }

to this:

_foo:
        fctiwz f0, f1
        stfiwx f0, 0, r4
        blr

instead of this:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        stw r2, 0(r4)
        blr

This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.

llvm-svn: 26447

is enabled.

llvm-svn: 26446

llvm-svn: 26445

llvm-svn: 26444

llvm-svn: 26443

llvm-svn: 26442

llvm-svn: 26441

implementing Regression/CodeGen/X86/mul-shift-reassoc.ll

llvm-svn: 26440

llvm-svn: 26439

llvm-svn: 26438

llvm-svn: 26437