Skip to content
  1. Mar 01, 2014
  2. Feb 28, 2014
    • Tom Stellard's avatar
      R600: Verify all instructions in the AsmPrinter on debug builds · 9b9e9264
      Tom Stellard authored
      Make a call to R600's implementation of verifyInstruction() to
      check that instructions are only using legal operands.
      
      llvm-svn: 202544
      9b9e9264
    • Tom Stellard's avatar
      R600/SI: Expand all v16[if]32 operations · d61a1c33
      Tom Stellard authored
      llvm-svn: 202543
      d61a1c33
    • Zoran Jovanovic's avatar
      Fixed operand of SC microMIPS instruction. · 285cc289
      Zoran Jovanovic authored
      llvm-svn: 202526
      285cc289
    • Zoran Jovanovic's avatar
      Fixed encoding of SYSCALL microMIPS instruction. · 7c6c36d9
      Zoran Jovanovic authored
      llvm-svn: 202523
      7c6c36d9
    • Zoran Jovanovic's avatar
      Revert revision 202518 because of wrong commit message. · d0a28900
      Zoran Jovanovic authored
      llvm-svn: 202521
      d0a28900
    • Zoran Jovanovic's avatar
      Fix operand of SC instruction. · 9874a2b1
      Zoran Jovanovic authored
      llvm-svn: 202518
      9874a2b1
    • Evgeniy Stepanov's avatar
      X86Operand is extracted into individual header. · e3804d48
      Evgeniy Stepanov authored
      X86Operand is extracted into individual header, because it allows to create an
      arbitrary memory operand and append it to MCInst. It'll be reused in X86 inline
      assembly instrumentation.
      
      Patch by Yuri Gorshenin.
      
      llvm-svn: 202496
      e3804d48
    • NAKAMURA Takumi's avatar
      Reorder Mips/MCTargetDesc/CMakeLists.txt. · cdb9fafa
      NAKAMURA Takumi authored
      llvm-svn: 202483
      cdb9fafa
    • Sasa Stankovic's avatar
      [mips] Add MipsNaClELFStreamer.cpp to CMakeLists.txt. · 441880f7
      Sasa Stankovic authored
      llvm-svn: 202482
      441880f7
    • Sasa Stankovic's avatar
      [mips] Implement NaCl sandboxing of indirect jumps: · 8c5736b9
      Sasa Stankovic authored
        * Align targets of indirect jumps to instruction bundle boundaries (in MI layer).
        * Add masking instructions before indirect jumps (in MC layer).
      
      Differential Revision: http://llvm-reviews.chandlerc.com/D2847
      
      llvm-svn: 202479
      8c5736b9
    • Hal Finkel's avatar
      Swap PPC isel operands to allow for 0-folding · b998915e
      Hal Finkel authored
      The PPC isel instruction can fold 0 into the first operand (thus eliminating
      the need to materialize a zero-containing register when the 'true' result of
      the isel is 0). When the isel is fed by a bit register operation that we can
      invert, do so as part of the bit-register-operation peephole routine.
      
      llvm-svn: 202469
      b998915e
    • Hal Finkel's avatar
      Trying to unbreak the darwin11 builder · 5cae2168
      Hal Finkel authored
      The CR bit tracking code broke PPC/Darwin; trying to get it working again...
      
      (the darwin11 builder, which defaults to the darwin ABI when running PPC tests,
      asserted when running test/CodeGen/PowerPC/inverted-bool-compares.ll)
      
      llvm-svn: 202459
      5cae2168
    • Hal Finkel's avatar
      Try to unbreak the C++11 build · b39a0475
      Hal Finkel authored
      Cannot use negative numbers in case statements without running afoul of -Wc++11-narrowing.
      
      llvm-svn: 202455
      b39a0475
    • Hal Finkel's avatar
      Add CR-bit tracking to the PowerPC backend for i1 values · 940ab934
      Hal Finkel authored
      This change enables tracking i1 values in the PowerPC backend using the
      condition register bits. These bits can be treated on PowerPC as separate
      registers; individual bit operations (and, or, xor, etc.) are supported.
      Tracking booleans in CR bits has several advantages:
      
       - Reduction in register pressure (because we no longer need GPRs to store
         boolean values).
      
       - Logical operations on booleans can be handled more efficiently; we used to
         have to move all results from comparisons into GPRs, perform promoted
         logical operations in GPRs, and then move the result back into condition
         register bits to be used by conditional branches. This can be very
         inefficient, because the throughput of these CR <-> GPR moves have high
         latency and low throughput (especially when other associated instructions
         are accounted for).
      
       - On the POWER7 and similar cores, we can increase total throughput by using
         the CR bits. CR bit operations have a dedicated functional unit.
      
      Most of this is more-or-less mechanical: Adjustments were needed in the
      calling-convention code, support was added for spilling/restoring individual
      condition-register bits, and conditional branch instruction definitions taking
      specific CR bits were added (plus patterns and code for generating bit-level
      operations).
      
      This is enabled by default when running at -O2 and higher. For -O0 and -O1,
      where the ability to debug is more important, this feature is disabled by
      default. Individual CR bits do not have assigned DWARF register numbers,
      and storing values in CR bits makes them invisible to the debugger.
      
      It is critical, however, that we don't move i1 values that have been promoted
      to larger values (such as those passed as function arguments) into bit
      registers only to quickly turn around and move the values back into GPRs (such
      as happens when values are returned by functions). A pair of target-specific
      DAG combines are added to remove the trunc/extends in:
        trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
      and:
        zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
      In short, we only want to use CR bits where some of the i1 values come from
      comparisons or are used by conditional branches or selects. To put it another
      way, if we can do the entire i1 computation in GPRs, then we probably should
      (on the POWER7, the GPR-operation throughput is higher, and for all cores, the
      CR <-> GPR moves are expensive).
      
      POWER7 test-suite performance results (from 10 runs in each configuration):
      
      SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
      MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
      MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
      SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
      SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
      SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
      
      SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
      MultiSource/Applications/lemon/lemon: 8% slowdown
      
      llvm-svn: 202451
      940ab934
  3. Feb 27, 2014
  4. Feb 26, 2014
Loading