- Mar 01, 2014
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Venkatraman Govindaraju authored
[Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the readability of the generated code. llvm-svn: 202563
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- Feb 28, 2014
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Tom Stellard authored
Make a call to R600's implementation of verifyInstruction() to check that instructions are only using legal operands. llvm-svn: 202544
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Tom Stellard authored
llvm-svn: 202543
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Zoran Jovanovic authored
llvm-svn: 202526
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Zoran Jovanovic authored
llvm-svn: 202523
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Zoran Jovanovic authored
llvm-svn: 202521
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Zoran Jovanovic authored
llvm-svn: 202518
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Evgeniy Stepanov authored
X86Operand is extracted into individual header, because it allows to create an arbitrary memory operand and append it to MCInst. It'll be reused in X86 inline assembly instrumentation. Patch by Yuri Gorshenin. llvm-svn: 202496
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NAKAMURA Takumi authored
llvm-svn: 202483
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Sasa Stankovic authored
llvm-svn: 202482
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Sasa Stankovic authored
* Align targets of indirect jumps to instruction bundle boundaries (in MI layer). * Add masking instructions before indirect jumps (in MC layer). Differential Revision: http://llvm-reviews.chandlerc.com/D2847 llvm-svn: 202479
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Hal Finkel authored
The PPC isel instruction can fold 0 into the first operand (thus eliminating the need to materialize a zero-containing register when the 'true' result of the isel is 0). When the isel is fed by a bit register operation that we can invert, do so as part of the bit-register-operation peephole routine. llvm-svn: 202469
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Hal Finkel authored
The CR bit tracking code broke PPC/Darwin; trying to get it working again... (the darwin11 builder, which defaults to the darwin ABI when running PPC tests, asserted when running test/CodeGen/PowerPC/inverted-bool-compares.ll) llvm-svn: 202459
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Hal Finkel authored
Cannot use negative numbers in case statements without running afoul of -Wc++11-narrowing. llvm-svn: 202455
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Hal Finkel authored
This change enables tracking i1 values in the PowerPC backend using the condition register bits. These bits can be treated on PowerPC as separate registers; individual bit operations (and, or, xor, etc.) are supported. Tracking booleans in CR bits has several advantages: - Reduction in register pressure (because we no longer need GPRs to store boolean values). - Logical operations on booleans can be handled more efficiently; we used to have to move all results from comparisons into GPRs, perform promoted logical operations in GPRs, and then move the result back into condition register bits to be used by conditional branches. This can be very inefficient, because the throughput of these CR <-> GPR moves have high latency and low throughput (especially when other associated instructions are accounted for). - On the POWER7 and similar cores, we can increase total throughput by using the CR bits. CR bit operations have a dedicated functional unit. Most of this is more-or-less mechanical: Adjustments were needed in the calling-convention code, support was added for spilling/restoring individual condition-register bits, and conditional branch instruction definitions taking specific CR bits were added (plus patterns and code for generating bit-level operations). This is enabled by default when running at -O2 and higher. For -O0 and -O1, where the ability to debug is more important, this feature is disabled by default. Individual CR bits do not have assigned DWARF register numbers, and storing values in CR bits makes them invisible to the debugger. It is critical, however, that we don't move i1 values that have been promoted to larger values (such as those passed as function arguments) into bit registers only to quickly turn around and move the values back into GPRs (such as happens when values are returned by functions). A pair of target-specific DAG combines are added to remove the trunc/extends in: trunc(binary-ops(binary-ops(zext(x), zext(y)), ...) and: zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...) In short, we only want to use CR bits where some of the i1 values come from comparisons or are used by conditional branches or selects. To put it another way, if we can do the entire i1 computation in GPRs, then we probably should (on the POWER7, the GPR-operation throughput is higher, and for all cores, the CR <-> GPR moves are expensive). POWER7 test-suite performance results (from 10 runs in each configuration): SingleSource/Benchmarks/Misc/mandel-2: 35% speedup MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown MultiSource/Applications/lemon/lemon: 8% slowdown llvm-svn: 202451
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- Feb 27, 2014
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Andrew Trick authored
This is a temporary workaround for native arm linux builds: PR18996: Changing regalloc order breaks "lencod" on native arm linux builds. llvm-svn: 202433
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Roman Divacky authored
expensive libcall. Also, Qp_neg is not implemented on at least FreeBSD. This is also what gcc is doing. llvm-svn: 202422
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Adrian Prantl authored
scan the register file for sub- and super-registers. No functionality change intended. (Tests are updated because the comments in the assembler output are different.) llvm-svn: 202416
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Richard Osborne authored
If a function returns a large struct by value return the first 4 words in registers and the rest on the stack in a location reserved by the caller. This is needed to support the xC language which supports functions returning an arbitrary number of return values. This is r202397 reapplied with a fix to avoid an uninitialized read of a member. llvm-svn: 202414
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Richard Osborne authored
No functionality change. This is r202396 reapplied with no changes. llvm-svn: 202413
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Rafael Espindola authored
We moved MCJIT to use native object formats a long time ago and R600 now uses ELF, so it was dead. llvm-svn: 202408
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Richard Osborne authored
These are causing test failures, revert for now. llvm-svn: 202398
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Richard Osborne authored
Summary: If a function returns a large struct by value return the first 4 words in registers and the rest on the stack in a location reserved by the caller. This is needed to support the xC language which supports functions returning an arbitrary number of return values. Reviewers: robertlytton Reviewed By: robertlytton CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2889 llvm-svn: 202397
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Richard Osborne authored
No functionality change. llvm-svn: 202396
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Richard Osborne authored
Summary: If the src, dst and size of a memcpy are known to be 4 byte aligned we can call __memcpy_4() instead of memcpy(). Reviewers: robertlytton Reviewed By: robertlytton CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2871 llvm-svn: 202395
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Richard Osborne authored
These instructions ignore the high bits of one of their input operands - try and use this to simplify the code. llvm-svn: 202394
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Richard Osborne authored
llvm-svn: 202393
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Craig Topper authored
llvm-svn: 202348
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Craig Topper authored
llvm-svn: 202347
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Craig Topper authored
[X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975. llvm-svn: 202345
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Michel Danzer authored
If the SI_KILL operand is constant, we can either clear the exec mask if the operand is negative, or do nothing otherwise. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 202337
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Michel Danzer authored
Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 202336
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Matt Arsenault authored
It is already fully handled in AMDGPUISelDAGToDAG. llvm-svn: 202312
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- Feb 26, 2014
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Quentin Colombet authored
The current approach to lower a vsetult is to flip the sign bit of the operands, swap the operands and then use a (signed) pcmpgt. psubus (unsigned saturating subtract) can be used to emulate a vsetult more efficiently: + case ISD::SETULT: { + // If the comparison is against a constant we can turn this into a + // setule. With psubus, setule does not require a swap. This is + // beneficial because the constant in the register is no longer + // destructed as the destination so it can be hoisted out of a loop. I also enable lowering via psubus in a few other cases where it's clearly beneficial: setule and setuge if minu/maxu cannot be used. rdar://problem/14338765 Patch by Adam Nemet <anemet@apple.com>. llvm-svn: 202301
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Aaron Ballman authored
llvm-svn: 202295
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Artyom Skrobov authored
ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block llvm-svn: 202257
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Daniel Sanders authored
Summary: This should fix the MCJIT unit tests that were broken by r201792 on the MIPS buildbot. MIPS currently uses the default implementation of sys::getHostCPUName() which always returns "generic". For now, we will accept "generic" and coerce it to "mips32" or "mips64" depending on the target architecture like we do for empty CPU names. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2878 llvm-svn: 202253
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Craig Topper authored
llvm-svn: 202240
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Craig Topper authored
llvm-svn: 202234
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Craig Topper authored
llvm-svn: 202233
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