and by restructuring the X86 version.

New I just have to move this to a common place :-)

llvm-svn: 43554

llvm-svn: 43234

llvm-svn: 43176

use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762

init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841

llvm-svn: 40757

still under discussion.

llvm-svn: 40549

TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704

llvm-svn: 37659

in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.

llvm-svn: 37179

llvm-svn: 36506

llvm-svn: 36324

llvm-svn: 35846

llvm-svn: 35840

flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573

llvm-svn: 35521

llvm-svn: 35406

not just the first letter.  No functionality change.

llvm-svn: 35322

llvm-svn: 35245

instructions (that would have to be split later)

llvm-svn: 35227

llvm-svn: 35196

llvm-svn: 35122

llvm-svn: 35075

        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664

llvm-svn: 33353