llvm-svn: 79833

MachineInstr and MachineOperand.  This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)

llvm-svn: 79813

llvm-svn: 79014

llvm-svn: 78970

llvm-svn: 78898

llvm-svn: 78779

llvm-svn: 78717

llvm-svn: 78666

llvm-svn: 78655

llvm-svn: 78377

llvm-svn: 78370

llvm-svn: 77781

  is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.

llvm-svn: 77701

llvm-svn: 77522

llvm-svn: 77422

Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024

Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod.

llvm-svn: 76995

llvm-svn: 76986

Also fixed up code to fully use the SoImm field for ADR on ARM mode.

llvm-svn: 76890

negative on an individual bases rather than basing on whether it's in thumb
mode.

llvm-svn: 76698

This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640

Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379

llvm-svn: 75067

llvm-svn: 74888

llvm-svn: 74658

llvm-svn: 74549

llvm-svn: 74543

After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420

llvm-svn: 71563

llvm-svn: 71562

will make it more obvious what it represents, and stop
it being confused with the StoreSize.

llvm-svn: 71349

llvm-svn: 64429

llvm-svn: 63161

suggested by Chris.

llvm-svn: 62099

llvm-svn: 58877

isReg, etc., from isRegister, etc.

llvm-svn: 57006

isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189

llvm-svn: 55779

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented

llvm-svn: 49809