-feature flag, instructions definitions, test cases

llvm-svn: 175196

The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.

In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter
slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and
add a special operand class for the parameter slots for type checking and
pretty printing.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175193

llvm-svn: 175190

llvm-svn: 175189

This patch doesn't introduce any functionality changes.

llvm-svn: 175187

inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi

llvm-svn: 175186

It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175183

This allows MachineInstScheduler to reorder them, and thus make scheduling more
efficient.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175182

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175181

This fixes a couple of regressions on (probably not just) cayman

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175180

llvm-svn: 175176

llvm-svn: 175173

If vector types have legal register classes, then LLVM bypasses LegalizeTypes
on them, which causes faults currently since the code to handle them isn't in
place.

This fixes test failures when AArch64 is the default target.

llvm-svn: 175172

Only comments affected. No code change at all.

llvm-svn: 175169

The parser will now accept instructions with alignment specifiers written like
    vld1.8  {d16}, [r0:64]
, while also still accepting the incorrect syntax
    vld1.8  {d16}, [r0, :64]

llvm-svn: 175164

llvm-svn: 175156

Add some legality checks for SETCC before introducing it in the DAG combiner post-operand legalization.

llvm-svn: 175149

Added a test.

llvm-svn: 175144

Fixes assertion failure in newly added lit test. Might just be a bandaid that
needs to be revisited.

llvm-svn: 175139

llvm-svn: 175133

register class to match the defining instruction.

llvm-svn: 175130

'and' instructions. This is a pattern that shows up a lot in ubsan binaries.

llvm-svn: 175128

up so that we can apply the direct object emitter patch. This patch
should be a nop right now and it's test is to not break what is already
there.
 

llvm-svn: 175126

CoalescerPairs. Also, make it take a CoalescerPair directly like other methods
of RegisterCoalescer.

llvm-svn: 175123

of the copy is a subregister def. The current code assumes that it can do a full
def of the destination register, but it is not checking that the def operand is
read-undef. It also doesn't clear the subregister index of the destination in
the new instruction to reflect the full subregister def.

These issues were found running 'make check' with my next commit that enables
rematerialization in more cases.

llvm-svn: 175122

llvm-svn: 175121

Since functions with internal linkage don't have language linkage, it is valid
to overload them:

extern "C" {
       static int foo();
       static int foo(int);
}

So we mangle them.

llvm-svn: 175120

llvm-svn: 175107

It's possible (e.g. after an LTO build) that an internal global may be used for
debugging purposes. If that's the case appending a '.b' to it makes it hard to
find that variable. Steal the name from the old GV before deleting it so that
they can find that variable again.

llvm-svn: 175104

llvm-svn: 175102

NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175096

Fixes PR15250!

llvm-svn: 175092

llvm-svn: 175088

instead of redefining separate instructions for them.

llvm-svn: 175086

displacements.
rdar://12974533

llvm-svn: 175083

llvm-svn: 175082

No functionality change.

llvm-svn: 175076

if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.

llvm-svn: 175073

Remove dead functions: renameRegister
Move private member variables from LDV to Impl
Remove ssp/uwtable from testing case

llvm-svn: 175072

llvm-svn: 175067