llvm-svn: 86366

MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.

llvm-svn: 86363

of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.

llvm-svn: 86360

llvm-svn: 86332

llvm-svn: 86330

  except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328

llvm-svn: 86325

Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers.  Coming soon, code to perform sret-demotion if return values cannot be lowered to registers

llvm-svn: 86324

was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0).  The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.

llvm-svn: 86319

llvm-svn: 86310

  load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304

llvm-svn: 86303

will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301

Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.

llvm-svn: 86294

llvm-svn: 86251

llvm-svn: 86199

implicit zero-extend.

llvm-svn: 86196

llvm-svn: 86149

llvm-svn: 86146

llvm-svn: 86114

llvm-svn: 86068

aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.

llvm-svn: 86064

llvm-svn: 86057

saved instructions even if no stack adjustment for those saves is needed.

llvm-svn: 86056

llvm-svn: 86050

The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.

With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.

llvm-svn: 86041

llvm-svn: 86019

llvm-svn: 85980

Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.

llvm-svn: 85965

llvm-svn: 85952

llvm-svn: 85914

llvm-svn: 85878

between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.

llvm-svn: 85874

llvm-svn: 85871

llvm-svn: 85870

llvm-svn: 85869

llvm-svn: 85861

llvm-svn: 85850

llvm-svn: 85847

constant pool so they don't get wrapped separately.

llvm-svn: 85844