llvm-svn: 89718

way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816.

* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.

llvm-svn: 89715

Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.

llvm-svn: 89711

It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.

llvm-svn: 89708

Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.

llvm-svn: 89706

llvm-svn: 89700

VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup.  VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.

llvm-svn: 89699

fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.

llvm-svn: 89694

{?,?,?,?} as op11_8 for VEXTd and VEXTq.

llvm-svn: 89693

ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.

llvm-svn: 89684

should be left unspecified now that Bob Wilson has fixed pr5470.

llvm-svn: 89676

llvm-svn: 89672

llvm-svn: 89618

llvm-svn: 89576

isn't necessary.

llvm-svn: 89568

backtraces.

llvm-svn: 89562

Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.

llvm-svn: 89542

llvm-svn: 89536

llvm-svn: 89478

constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.

llvm-svn: 89473

llvm-svn: 89443

llvm-svn: 89440

Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.

llvm-svn: 89423

llvm-svn: 89414

assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.

llvm-svn: 89403

llvm-svn: 89396

fully specified at this level.  Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.

llvm-svn: 89377

llvm-svn: 89369

llvm-svn: 89337

llvm-svn: 89328

llvm-svn: 89326

llvm-svn: 89325

llvm-svn: 89218

llvm-svn: 89214

contents of the block to be duplicated.  Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.

llvm-svn: 89187

llvm-svn: 89143

alignment imm (in the same way). Fix asmprinting for non-darwin platforms.

llvm-svn: 89137

distinguish between them and the more generic instructions (add, mov, and ldr).

llvm-svn: 89108

is analyzable so it can be updated. If it's not, be safe and don't move the
block.

llvm-svn: 89022

0b1110 (ALways).  This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.

llvm-svn: 89000