Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD.

llvm-svn: 56594

llvm-svn: 56593

llvm-svn: 56588

llvm-svn: 56587

llvm-svn: 56586

llvm-svn: 56585

llvm-svn: 56582

llvm-svn: 56581

llvm-svn: 56580

llvm-svn: 56578

llvm-svn: 56577

llvm-svn: 56576

llvm-svn: 56575

llvm-svn: 56574

llvm-svn: 56573

llvm-svn: 56572

SPU section handling is really huge mess. Replace remaining TAI calls for sections with explicit names in order not to block existing backends during section handling migration. SPU folks! Please consider using new section handling facility someday.

llvm-svn: 56570

llvm-svn: 56569

llvm-svn: 56568

llvm-svn: 56535

llvm-svn: 56527

Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.

llvm-svn: 56526

Do not check isDeclaration() in hasNote(). It is clients' responsibility.

llvm-svn: 56524

llvm-svn: 56513

Function Notes also. Function notes are stored at index ~0.

llvm-svn: 56511

object. This will be needed to support debug info.

llvm-svn: 56508

instruction opcodes are now numbered. No functionality change.

llvm-svn: 56497

llvm-svn: 56495

X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow
it to be reused by FastISel.

llvm-svn: 56494

llvm-svn: 56486

llvm-svn: 56483

llvm-svn: 56477

llvm-svn: 56475

default.

llvm-svn: 56471

llvm-svn: 56469

llvm-svn: 56453

Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.

llvm-svn: 56436

llvm-svn: 56419

sarl    $3, %ecx

instead of:

movl    $3, %ecx
sarl    %cl, %edx

This shrinks fast isel 176.gcc by about 2000 instructions (.3%)

llvm-svn: 56413

compute the maximum element directly.

llvm-svn: 56411