llvm-svn: 25058

llvm-svn: 25005

* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997

llvm-svn: 24989

llvm-svn: 24934

llvm-svn: 24901

llvm-svn: 24879

llvm-svn: 24870

llvm-svn: 24819

one for use with extload, one for use with sextload and zextload, which
are integer only.

llvm-svn: 24814

llvm-svn: 24787

llvm-svn: 24748

* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726

llvm-svn: 24723

llvm-svn: 24715

OtherVT, it cannot be compare to type of 1st operand which is an integer type.

llvm-svn: 24713

llvm-svn: 24703

llvm-svn: 24700

llvm-svn: 24664

llvm-svn: 24662

llvm-svn: 24660

them in the PPC backend, to simplify some logic out of Select and
SelectAddr.

llvm-svn: 24657

llvm-svn: 24656

* Added X86 dec patterns.

llvm-svn: 24654

must be a pointer.  This removes a type check out of the code generated by
tblgen for load matching.

llvm-svn: 24650

llvm-svn: 24638

being shifted.  Don't assume they are.

llvm-svn: 24598

  chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
  chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.

llvm-svn: 24586

llvm-svn: 24389

selecting ints to IA64, and a few other ia64 bits and pieces

llvm-svn: 24147

llvm-svn: 24132

to make it easy to use them.  This lets you write patterns like:

(set PRRC:$rd, (setne GPRC:$rS, imm:$SH))

and stuff.

llvm-svn: 24009

llvm-svn: 23990

llvm-svn: 23851

llvm-svn: 23848

llvm-svn: 23733

llvm-svn: 23726

can be used by other targets.  For those targets that want to use it,
have at.  :)

llvm-svn: 23680