Commits · f9ab416d7066d75ae1e42c706687926840454726 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Feb 27, 2016
- WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC · f9ab416d
  Duncan P. N. Exon Smith authored Feb 27, 2016
  f9ab416d
- WebAssembly: fix build · 13d3b9b7
  JF Bastien authored Feb 27, 2016
  13d3b9b7
- Tidyup for loops - don't repeat upper limit evaluation if you don't have to. NFCI. · 9e10b165
  Simon Pilgrim authored Feb 27, 2016
  9e10b165
- The patch adds missing registers and instructions to complete all the... · 053826af
  Chris Dewhurst authored Feb 27, 2016
  053826af
- Strip trailing whitespace. NFCI. · 3b42ca07
  Simon Pilgrim authored Feb 27, 2016
  3b42ca07
- AMDGPU: Split vi-insts subtarget feature · 9d82ee75
  Matt Arsenault authored Feb 27, 2016
  9d82ee75
- AMDGPU: Add s_sleep intrinsic · 274d34e7
  Matt Arsenault authored Feb 27, 2016
  274d34e7
- AMDGPU: Implement readcyclecounter · 61738cbc
  Matt Arsenault authored Feb 27, 2016
  61738cbc
- CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC · 3ac9cc61
  Duncan P. N. Exon Smith authored Feb 27, 2016
  3ac9cc61
Feb 26, 2016
- [X86] Fix a stale comment. NFC. · ffcab7bf
  Ahmed Bougacha authored Feb 26, 2016
  ffcab7bf
- [X86] Remove the unused SDTX86atomicBinary. NFC. · 55e15928
  Ahmed Bougacha authored Feb 26, 2016
  55e15928
- Strip trailing whitespace. NFCI. · 4d1a0883
  Simon Pilgrim authored Feb 26, 2016
  4d1a0883
- [PPC] Legalize FNEG on PPC when possible · 915c5ece
  Kit Barton authored Feb 26, 2016
  915c5ece
- Fix spelling. NFCI. · 10e3ca2c
  Simon Pilgrim authored Feb 26, 2016
  10e3ca2c
- Power9] Implement new vsx instructions: compare and conversion · 93612ec5
  Kit Barton authored Feb 26, 2016
  93612ec5
- [x86] refactor to eliminate duplicated code; NFCI · 51488ed2
  Sanjay Patel authored Feb 26, 2016
  51488ed2
- Fix Sparc 32bit Lowering to rebundle up v2i32 values. · 2993854b
  Nirav Dave authored Feb 26, 2016
  2993854b
- [x86, AVX] fold 'isPositive' 256-bit vector integer operations (PR26701) · 155193c3
  Sanjay Patel authored Feb 26, 2016
  155193c3
- [x86, SSE] fold 'isPositive' vector integer operations (PR26701) · 4402a32b
  Sanjay Patel authored Feb 26, 2016
  4402a32b
- Reverting breaking change. Sorry. · 829b104d
  Chris Dewhurst authored Feb 26, 2016
  829b104d
- Reviewed at reviews.llvm.org/D17133 · 9c3bf91d
  Chris Dewhurst authored Feb 26, 2016
  9c3bf91d
- Initial test commit only · 6456376f
  Chris Dewhurst authored Feb 26, 2016
  6456376f
- [AMDGPU] Assembler: Basic support for MIMG · 2f684f13
  Nikolay Haustov authored Feb 26, 2016
  2f684f13
- [AArch64] Slight cleanup in FPLoadBalancing · 4eba0154
  James Molloy authored Feb 26, 2016
  4eba0154
- [X86] Null out some redundant patterns for masked vector register to register... · c9293499
  Craig Topper authored Feb 26, 2016
  c9293499
- [X86] Add test cases for r261977 and fix a grammatical error. · d50b5f8a
  Craig Topper authored Feb 26, 2016
  d50b5f8a
- [X86] Remove a couple returns after llvm_unreachables. NFC · 4d187630
  Craig Topper authored Feb 26, 2016
  4d187630
- [X86] Use inclusive ranges for XMM/YMM/ZMM registers in is32Extended and isX86_64ExtendedReg. NFC · a11be0be
  Craig Topper authored Feb 26, 2016
  a11be0be
- [X86] Explicitly diagnose use of %xmm16-%xmm31, %ymm16-%ymm31 and... · 29c22733
  Craig Topper authored Feb 26, 2016
  29c22733
Feb 25, 2016
- Reformatted a comment to fit the 80 column limit. NFC. · 602ba70a
  David L Kreitzer authored Feb 25, 2016
  602ba70a
- Introduce analysis pass to compute PostDominators in the new pass manager. NFC · 3f978407
  Hongbin Zheng authored Feb 25, 2016
  3f978407
- ARM: disallow pc as a base register in Thumb2 memory ops. · aa35bd26
  Tim Northover authored Feb 25, 2016
  aa35bd26
- [AArch64] Clean up callee-save CFI emission. NFC. · 62d47250
  Geoff Berry authored Feb 25, 2016
  62d47250
- [AMDGPU] Disassembler: Support for all VOP1 instructions. · 161a158e
  Nikolay Haustov authored Feb 25, 2016
  161a158e
- AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx .... · 45ef10f1
  Igor Breger authored Feb 25, 2016
  45ef10f1
- [mips][microMIPS] Implement DINSU, DINSM, DINS instructions · 46458d0b
  Hrvoje Varga authored Feb 25, 2016
  46458d0b
- [AMDGPU] Assembler: Simplify handling of optional operands · 2e4c7297
  Nikolay Haustov authored Feb 25, 2016
  2e4c7297
- [X86][SSE3] Added combine support for MOVDDUP/MOVSHDUP/MOVSLDUP target shuffles · e4178ae5
  Simon Pilgrim authored Feb 25, 2016
  e4178ae5
- Revert r261742, "[AMDGPU] Assembler: Simplify handling of optional operands" · 3d3d0f41
  NAKAMURA Takumi authored Feb 25, 2016
  3d3d0f41
- Optimized loading (zextload) of i1 value from memory. · e5bbca6a
  Elena Demikhovsky authored Feb 25, 2016
  e5bbca6a