llvm-svn: 37289

llvm-svn: 37288

for a target-dependent default with a command-line override; this way
should be generally usable.

llvm-svn: 37285

llvm-svn: 37270

it occurs for multiple landing pads.

llvm-svn: 37267

llvm-svn: 37249

this case, the xform introduces an extra operation).  This compiles
PowerPC/compare-duplicate.ll into:

_test:
        subf r2, r3, r4
        cmplw cr0, r2, r3
        bne cr0, LBB1_2 ;F

instead of:

_test:
        slwi r2, r3, 1
        subf r3, r3, r4
        cmplw cr0, r4, r2
        bne cr0, LBB1_2 ;F

This is target independent of course.

llvm-svn: 37246

llvm-svn: 37237

llvm-svn: 37236

llvm-svn: 37235

llvm-svn: 37233

llvm-svn: 37231

llvm-svn: 37230

llvm-svn: 37227

llvm-svn: 37200

llvm-svn: 37198

llvm-svn: 37195

llvm-svn: 37190

i128 integers.  The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.

llvm-svn: 37169

add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets

llvm-svn: 37168

llvm-svn: 37134

llvm-svn: 37130

llvm-svn: 37126

llvm-svn: 37121

runtime.

llvm-svn: 37104

This fixes PR1423

llvm-svn: 37102

llvm-svn: 37097

llvm-svn: 37094

llvm-svn: 37092

llvm-svn: 37089

llvm-svn: 37086

llvm-svn: 37084

llvm-svn: 37071

test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll

llvm-svn: 37069

llvm-svn: 37064

CodeGen/PowerPC/fneg.ll into:

_t4:
        fmul f0, f3, f4
        fmadd f1, f1, f2, f0
        blr

instead of:

_t4:
        fneg f0, f3
        fmul f0, f0, f4
        fmsub f1, f1, f2, f0
        blr

llvm-svn: 37054

llvm-svn: 37052

v1 =
r2 = move v1
   = op r2<kill>
...
r2 = move v1
   = op r2<kill>

Clear the first r2 kill if v1 and r2 are joined.

llvm-svn: 37050

When marking a register as being implicitly defined, make sure to clear its partial use info as well.

llvm-svn: 37046

just aids in readability and debugability of the output. No functional change.

llvm-svn: 37037