llvm-svn: 133215

llvm-svn: 133214

llvm-svn: 133213

because the Angled directories and the System directories were not being uniqued 
together, breaking #include_next.  I'll see about a testcase, but it will be insane.

llvm-svn: 133212

llvm-svn: 133211

In Thumb mode we cannot handle GPR virtual registers, even though some
instructions can. When isel is lowering a CopyFromReg, it should limit
itself to subclasses of getRegClassFor(VT).

<rdar://problem/9624323>

llvm-svn: 133210

(even though it is incomplete type) because gcc
says so. // rdar://9622422

llvm-svn: 133208

llvm-svn: 133207

options just to pass to ld).

llvm-svn: 133206

llvm-svn: 133205

  For the print_stacktrace(thread, string_buffer = False) function, if we have debug info
  for a frame function, let's also emit the args for the current function.

o TestFrameUtils.py:

  Add stronger assertTrue for frame0's args.

o TestPrintStackTraces.py:

  Launch the inferior with ["abc", "xyz"] and expect '(int)argc=3' in the stack traces, since
  by design the inferior is built with debug info.

llvm-svn: 133204

No functional change was intended.

llvm-svn: 133202

llvm-svn: 133201

Reviewed by chapuni. Sorry for breaking.

llvm-svn: 133200

Reviewed by chapuni. Sorry for breaking.

llvm-svn: 133199

llvm-svn: 133197

Add a new warning when a NULL constant is used in arithmetic operations.  The warning will fire on cases such as:

int x = 1 + NULL;

llvm-svn: 133196

llvm-svn: 133195

llvm-svn: 133194

aren't getting debug info from the liblldb-core.a file in our build server
builds.

llvm-svn: 133193

This limits the # address spaces to 2^23, which should be good enough.

llvm-svn: 133192

the SubclassData field, saving a word.

llvm-svn: 133191

llvm-svn: 133190

llvm-svn: 133189

than trying to insert them immediately after the invoke.

llvm-svn: 133188

llvm-svn: 133187

I think PBQP could use RegisterClassInfo, but it didn't fit neatly with
the external interfaces that PBQP uses, so I'll leave that to Lang.

llvm-svn: 133186

BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.

llvm-svn: 133184

llvm-svn: 133183

getLVForNamespaceScopeDecl(). // rdar://9609649

llvm-svn: 133182

llvm-svn: 133181

constants. Fixes PR10145.

llvm-svn: 133179

Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand.  This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.

llvm-svn: 133178

This avoids the manual filtering of reserved registers and removes the
dependency on allocation_order_begin().

Palliative care...

llvm-svn: 133177

llvm-svn: 133176

llvm-svn: 133175

llvm-svn: 133174

__builtin_ versions of these functions as well as the normal function
versions, so that it works on platforms where memset/memcpy/memmove
are macros that map down to the builtins (e.g., Darwin). Fixes
<rdar://problem/9372688>.

llvm-svn: 133173

llvm-svn: 133172

llvm-svn: 133171