llvm-svn: 32068

llvm-svn: 32057

llvm-svn: 32034

created intrinsics have the right integer types.  This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll

llvm-svn: 32024

llvm-svn: 32019

llvm-svn: 31970

llvm-svn: 31969

llvm-svn: 31966

of opcode and number of operands.

llvm-svn: 31947

llvm-svn: 31902

llvm-svn: 31884

llvm-svn: 31882

Also, valist should create a pointer RC reg class value, not a GPRC value.

llvm-svn: 31840

llvm-svn: 31839

llvm-svn: 31838

The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model.  This fixes assembler errors when compiling 403.gcc with
tail merging enabled.

Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion.  Only if branches need expansion are instructions rewritten
and created.  This should make branch select faster, and eliminates the
Bxx instructions from the .td file.

llvm-svn: 31837

issues to the ground.

llvm-svn: 31836

value and CR reg #.  This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(

llvm-svn: 31835

llvm-svn: 31834

llvm-svn: 31833

llvm-svn: 31828

2. Offsets on 64-bit stores are still in bytes.

llvm-svn: 31824

llvm-svn: 31823

llvm-svn: 31805

llvm-svn: 31799

llvm-svn: 31797

This is a general clean up of the PowerPC ABI.  Address several problems and
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.

llvm-svn: 31792

before printing it.

llvm-svn: 31791

llvm-svn: 31785

llvm-svn: 31778

llvm-svn: 31776

llvm-svn: 31775

llvm-svn: 31774

llvm-svn: 31771

Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).

llvm-svn: 31770

llvm-svn: 31765

addrmodes.

llvm-svn: 31757

llvm-svn: 31752

pair for cleanliness.  Add instructions for PPC32 preinc-stores with commented
out patterns.  More improvement is needed to enable the patterns, but we're
getting close.

llvm-svn: 31749

llvm-svn: 31736