copyfromreg nodes.  Clearly useful!

llvm-svn: 26559

llvm-svn: 26558

llvm-svn: 26554

function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.

llvm-svn: 26552

bounds its lifetime.

llvm-svn: 26550

llvm-svn: 26548

llvm-svn: 26545

It's causing an infinite loop compiling ldecod on x86 / Darwin.

llvm-svn: 26544

llvm-svn: 26543

llvm-svn: 26542

fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)

This allows us to compile CodeGen/PowerPC/addi-reassoc.ll into:

_test1:
        slwi r2, r4, 4
        add r2, r2, r3
        lwz r3, 36(r2)
        blr
_test2:
        mulli r2, r4, 5
        add r2, r2, r3
        lbz r2, 11(r2)
        extsb r3, r2
        blr

instead of:

_test1:
        addi r2, r4, 2
        slwi r2, r2, 4
        add r2, r3, r2
        lwz r3, 4(r2)
        blr
_test2:
        addi r2, r4, 2
        mulli r2, r2, 5
        add r2, r3, r2
        lbz r2, 1(r2)
        extsb r3, r2
        blr

llvm-svn: 26535

llvm-svn: 26509

llvm-svn: 26505

llvm-svn: 26504

llvm-svn: 26502

llvm-svn: 26501

llvm-svn: 26500

llvm-svn: 26498

llvm-svn: 26493

llvm-svn: 26479

PR709, and paving the way for future progress.

llvm-svn: 26476

  a predecessor appearing more than once in the operand list was counted as
  multiple predecessor; priority1 should be updated during scheduling;
  CycleBound was updated after the node is inserted into priority queue; one
  of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
  operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
  predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
        .text
        .align  4
        .globl  _f
_f:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        movl %eax, %edx
        imull %ecx, %edx
        imull %eax, %eax
        imull %ecx, %ecx
        addl %eax, %ecx
        leal (%ecx,%edx,2), %eax
        ret

  It is also a slight performance win (1% - 3%) for most tests.

llvm-svn: 26470

llvm-svn: 26466

span multiple lines.

llvm-svn: 26463

in the dag combiner on 176.gcc on x86.

llvm-svn: 26459

debug forms.

llvm-svn: 26455

llvm-svn: 26454

llvm-svn: 26453

llvm-svn: 26452

llvm-svn: 26451

llvm-svn: 26443

llvm-svn: 26441

implementing Regression/CodeGen/X86/mul-shift-reassoc.ll

llvm-svn: 26440

llvm-svn: 26436

- All abstrct vector nodes must have # of elements and element type as their
first two operands.

llvm-svn: 26432

Add array of debug descriptor support.

llvm-svn: 26428

unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }

to:

_foo4:
        lbz r3,1(r3)
        blr
_foo5:
        lbz r3,1(r3)
        blr

not:

_foo4:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr
_foo5:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

llvm-svn: 26419

unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
        lbz r3, 3(r3)
        blr

instead of:

_foo3:
        lwz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

and:

unsigned short foo2(float a) { return a; }

as:
_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lhz r3, -2(r1)
        blr

instead of:

_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

llvm-svn: 26417

llvm-svn: 26416

llvm-svn: 26410