an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900

llvm-svn: 104899

llvm-svn: 104897

llvm-svn: 104891

should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.

llvm-svn: 104883

to update the jmpbuf in the presence of VLAs.

llvm-svn: 104862

TableGen shortly.

llvm-svn: 104754

ISD::. No functional change.

llvm-svn: 104734

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704

llvm-svn: 104670

Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.

llvm-svn: 104667

llvm-svn: 104661

This reverts commit 104654.

llvm-svn: 104660

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654

Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.

llvm-svn: 104653

Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.

llvm-svn: 104652

SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627

Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))

llvm-svn: 104588

llvm-svn: 104587

I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.

llvm-svn: 104583

Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.

llvm-svn: 104582

llvm-svn: 104580

llvm-svn: 104573

llvm-svn: 104571

version of t2MVN already allowed that, but not the register versions.

llvm-svn: 104570

llvm-svn: 104564

structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563

llvm-svn: 104544

Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.

llvm-svn: 104531

llvm-svn: 104518

Add assertions in places that depend on consecutive indices.

llvm-svn: 104510

from ARMRegisterInfo.h

llvm-svn: 104508

llvm-svn: 104455

llvm-svn: 104421

Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419

copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.

llvm-svn: 104415

Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).

llvm-svn: 104307

Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.

llvm-svn: 104293

This fixes the remaining issue with pr7167.

llvm-svn: 104257

Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.

llvm-svn: 104147