llvm-svn: 115373

llvm-svn: 115370

llvm-svn: 115365

Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs.  For now,
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.

llvm-svn: 115364

been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.

llvm-svn: 115360

llvm-svn: 115354

llvm-svn: 115353

llvm-svn: 115350

llvm-svn: 115344

llvm-svn: 115342

Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.

llvm-svn: 115341

llvm-svn: 115339

Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.

llvm-svn: 115332

llvm-svn: 115314

SingleSource/Regression/C/casts.c.

llvm-svn: 115246

conversion heuristics to the old-style ones.

llvm-svn: 115239

llvm-svn: 115225

llvm-svn: 115203

llvm-svn: 115193

vs. ELF

llvm-svn: 115180

llvm-svn: 115176

llvm-svn: 115160

for the dwarf .loc support to emit dwarf line number tables.

llvm-svn: 115153

llvm-svn: 115149

llvm-svn: 115147

llvm-svn: 115136

llvm-svn: 115135

Small test for sanity check of resulting ARM .s file.
Tested against -r115129.

llvm-svn: 115133

Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.

llvm-svn: 115130

I added a new file ARMAsmBackend which stubs out in similar ways to
the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)

Tested against -r115126

llvm-svn: 115129

to an empty PrintSpecial()

llvm-svn: 115128

(Kill the dead non-MC asm printer for the ARM target.)

llvm-svn: 115127

1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.

llvm-svn: 115121

for generic call handling.

llvm-svn: 115105

pipeline forwarding path.

llvm-svn: 115098

a context.

llvm-svn: 115094

which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.

llvm-svn: 115066

LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned.  Radar 8489376.

llvm-svn: 115047

llvm-svn: 115043

One Printer to lower them all and in the back end bind them.


(Remove option to use the old non-MC asm printer.)

llvm-svn: 115038