calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856

which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855

it would be a bit too big :-)

llvm-svn: 117849

llvm-svn: 117848

"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831

directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830

llvm-svn: 117824

llvm-svn: 117823

llvm-svn: 117822

llvm-svn: 117821

for shl.  Caught by inspection.

llvm-svn: 117820

llvm-svn: 117819

llvm-svn: 117818

llvm-svn: 117817

llvm-svn: 117816

just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815

it claiming not to have side-effects is no longer needed.

llvm-svn: 117789

llvm-svn: 117787

llvm-svn: 117785

consider it to be readonly.  In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment).  This fixes PR8279.

llvm-svn: 117783

llvm-svn: 117782

llvm-svn: 117773

llvm-svn: 117771

llvm-svn: 117769

llvm-svn: 117766

llvm-svn: 117765

a basic block.

llvm-svn: 117764

elsewhere.

llvm-svn: 117763

llvm-svn: 117762

llvm-svn: 117761

There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756

llvm-svn: 117753

conditional. Check for those instructions explicitly.

llvm-svn: 117747

llvm-svn: 117745

llvm-svn: 117742

llvm-svn: 117741

llvm-svn: 117740

encoder functions.

llvm-svn: 117738

llvm-svn: 117737

just

.type   foo,@object

will produce an undefined reference to foo. On the other hand, a file with
just

.weakref bar, foo

will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.

With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.

This is in preparation for a patch implementing .weakref.

llvm-svn: 117735