When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384

 - Sorry, I can't help myself.

 - No intended functionality change.

llvm-svn: 74742

Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.

TableGen has been taught to generate the lists from instruction definitions.

llvm-svn: 57722

CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags. 

This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.

llvm-svn: 49123

llvm-svn: 45822

occured in a pattern, but failed miserably.  The new code works for
any instruction that has a store in its pattern, including all the 
x86 mem op mem instructions.

The only target-independent code that uses this is branch folding,
so this won't change anything in practice.

llvm-svn: 45648

rearrange some code to allow inferring instr info from the pattern of the instr, but don't do so yet.

llvm-svn: 45647

llvm-svn: 45644

llvm-svn: 45643

llvm-svn: 45642

llvm-svn: 45640

llvm-svn: 45419

to extend.

llvm-svn: 31481

llvm-svn: 31464

llvm-svn: 31333

llvm-svn: 24122

llvm-svn: 24074

in one way: the generated tables require dynamic initialization for the
register classes.  This will be fixed in a future patch.

llvm-svn: 22919

LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data.  This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.

This should speed up the register allocator as well by reducing the dcache
footprint for this static data.

llvm-svn: 22879

llvm-svn: 21428

and work better with VC++.  Patch contributed by Morten Ofstad!

llvm-svn: 17281

an instance of the Instruction tablegen class.

llvm-svn: 15385

llvm-svn: 9903

llvm-svn: 9305

llvm-svn: 8875

llvm-svn: 7627

llvm-svn: 7543

llvm-svn: 7515