The primary advantage is that loop optimizations will be applied in a
stable order. This helps debugging and unit test creation. It is also
a better overall implementation without pathologically bad performance
on deep functions.

On large functions (llvm-stress --size=200000 | opt -loops)
Before: 0.1263s
After:  0.0225s

On deep functions (after tweaking llvm-stress, thanks Nadav):
Before: 0.2281s
After:  0.0227s

See r158790 for more comments.

The loop tree is now consistently generated in forward order, but loop
passes are applied in reverse order over the program. If we have a
loop optimization that prefers forward order, that can easily be
achieved by adding a different type of LoopPassManager.

llvm-svn: 159183

llvm-svn: 159182

Make sure type is not extended or untyped before create a constant of the type. No test case. Found by inspection.

llvm-svn: 159179

llvm-svn: 159178

Make some ugly hacks for inline asm operands which name a specific register a bit more thorough.  PR13196.

llvm-svn: 159176

revert my previous commit (r159173), since as Eli pointed out, it's perfectly ok to mark realloc as noalias

llvm-svn: 159175

do not set realloc() as NotAlias, since it can return the same pointer. This whole thing should be upgraded to use the MemoryBuiltin interface anyway..

llvm-svn: 159173

More condition codes are included when deciding whether to remove cmp after
a sub instruction. Specifically, we extend from GE|LT|GT|LE to 
GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we
should be able to replace with "sub a, b; movls".

rdar: 11725965
llvm-svn: 159166

Define DAGOperand, an empty base class for RegisterClass and Operand.  This allows one to write multiclasses that are polymorphic over both registers and non-register operands.

llvm-svn: 159162

the call correctly even in the case where it is an invoke. This
fixes rdar://11714057.

llvm-svn: 159157

Verify that all paths from the entry block to a virtual register read
pass through a def. Enable this check even when MRI->isSSA() is false.

Verify that the live range of a virtual register is live out of all
predecessor blocks, even for PHI-values.

This requires that PHIElimination sometimes inserts IMPLICIT_DEF
instruction in predecessor blocks.

llvm-svn: 159150

Implicitly defined virtual registers can simply have the <undef> bit set
on all uses, and copies can be turned into implicit defs recursively.

Physical registers are a bit trickier. We handle the common case where a
physreg def is used by a nearby instruction in the same basic block. For
more complicated cases, just leave the IMPLICIT_DEF instruction in.

llvm-svn: 159149

 - simplifycfg:  invoke undef/null -> unreachable
 - instcombine:  invoke new  -> invoke expect(0, 0)  (an arbitrary NOOP intrinsic;  only done if the allocated memory is unused, of course)
 - verifier:  allow invoke of intrinsics  (to make the previous step work)

llvm-svn: 159146

llvm-svn: 159145

llvm-svn: 159144

Fix 'sys::IdentifyFileType' to work with big and little endian byte orderings
when reading the ELF object file type.

Initial patch by Stefan Hepp.

llvm-svn: 159138

hidden. Being linkonce_odr guarantees that it is available in every dso that
needs it. Being a constant/function with unnamed_addr guarantees that the
copies don't have to be merged.

llvm-svn: 159136

The name (and comment describing) of llvm::GetFirstDebuigLocInBasicBlock no longer represents what the function does. Therefore, the function is removed and its functionality is folded into the only place in the code-base where it was being used.

llvm-svn: 159133

Add SSE2 predicate to CVTPS2PD instructions. Doesn't matter much because there are no patterns in the instruction.

llvm-svn: 159127

Remove codegen only instruction in favor of one that has the same definition. Make some pattern operands more explicit about types.

llvm-svn: 159126

advertising complete support w/o alignas implemented, and its
implementation of alignas in the latest versions is so convoluted as to
be unusable.

llvm-svn: 159125

When a PHI use is <undef>, don't emit a copy in the predecessor block,
but insert an IMPLICIT_DEF instruction instead. This ensures that
virtual register uses are always jointly dominated by defs, even if some
of them are IMPLICIT_DEF.

llvm-svn: 159121

When the source register to a 2-addr instruction is undefined, there is
no need to attempt any transformations - simply replace the source
register with the destination register.

This also comes up when lowering IMPLICIT_DEF instructions - make sure
the <undef> flag is moved to the new partial register def operand:

  %vreg8<def> = INSERT_SUBREG %vreg9<undef>, %vreg0<kill>, sub_16bit
rewrite undef:
  %vreg8<def> = INSERT_SUBREG %vreg8<undef>, %vreg0<kill>, sub_16bit
convert to:
  %vreg8:sub_16bit<def,read-undef> = COPY %vreg0<kill>

llvm-svn: 159120

The function live-out registers must be live at all function returns,
and %RCX is only used by eh.return. When a function also has a normal
return, only %RAX holds a return value.

This fixes PR13188.

llvm-svn: 159116

llvm-svn: 159112

These are used as the result of comparisons, and often handled differently from larger integer types.

llvm-svn: 159111

the safety check to look for the same type we're going to actually cast to.
Fixes PR13180!

llvm-svn: 159110

llvm-svn: 159109

llvm-svn: 159108

llvm-svn: 159107

llvm-svn: 159106

llvm-svn: 159105

llvm-svn: 159104

FYI, two arguments of strerror_s() is provided in C++ on msvc.

llvm-svn: 159103

FIXME: Shall we put *.def(s) to the folder?
llvm-svn: 159102

msvc mis-infers ParentTy(RHS) to (const RangesCollectionTy &).

llvm-svn: 159101

llvm-svn: 159100

llvm-svn: 159099

llvm-svn: 159098

VMCore/CMakeLists.txt: [CMake][MSVC] Add "/Og-" to Function.cpp on msvc10. Otherwise, it took over 20 minutes to compile.

FIXME: Suppressing optimizations to core libraries would not be good thing.
llvm-svn: 159097