llvm-svn: 132419

floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404

Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

llvm-svn: 132398

patch to TargetLowering.cpp.  rdar://problem/5660695

llvm-svn: 132388

directives.

Fixes PR9826.

llvm-svn: 132317

same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

llvm-svn: 132314

subregisters of the 64 bit ones.

llvm-svn: 132313

llvm-svn: 132238

llvm-svn: 132230

was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.

llvm-svn: 132225

The register allocators know to filter reserved registers from the allocation
orders, so we don't need all of this boilerplate.

llvm-svn: 132199

refer to them.

I tested this with both check-all and the gdb testsuite.

llvm-svn: 132187

crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].

llvm-svn: 132163

llvm-svn: 132108

rdar://problem/6920088

llvm-svn: 132105

Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.

The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .

llvm-svn: 132099

llvm-svn: 132062

MSVC doesn't support 64 bit enum. 
OpcodeMask is not used anywhere in the code base.

llvm-svn: 132057

LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.

llvm-svn: 132033

scheme uses internally. Implement it for x86 (the only architecture that LLVM
supports for which this matters right now).

llvm-svn: 131969

  non-zero.
- Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension
  when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero.

rdar://9490949

llvm-svn: 131948

llvm-svn: 131874

llvm-svn: 131801

is already in GR64 for the same reasons. Since it isn't allocatable it can't cause
any problems.

llvm-svn: 131787

llvm-svn: 131764

rdar://problem/8614450

llvm-svn: 131746

llvm-svn: 131730

llvm-svn: 131709

llvm-svn: 131708

llvm-svn: 131689

Fixes rdar://9218925
Fixes PR9601

llvm-svn: 131682

Fixes PR9934.

We really need to start tblgening the relocation info :-(

llvm-svn: 131669

llvm-svn: 131664

llvm-svn: 131654

pseudos.  rdar://problem/8614450

llvm-svn: 131641

llvm-svn: 131597

llvm-svn: 131596

uses them.

llvm-svn: 131591

Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible.

llvm-svn: 131560

llvm-svn: 131476