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  1. Mar 21, 2008
    • Duncan Sands's avatar
      Introduce a new node for holding call argument · d97eea37
      Duncan Sands authored
      flags.  This is needed by the new legalize types
      infrastructure which wants to expand the 64 bit
      constants previously used to hold the flags on
      32 bit machines.  There are two functional changes:
      (1) in LowerArguments, if a parameter has the zext
      attribute set then that is marked in the flags;
      before it was being ignored; (2) PPC had some bogus
      code for handling two word arguments when using the
      ELF 32 ABI, which was hard to convert because of
      the bogusness.  As suggested by the original author
      (Nicolas Geoffray), I've disabled it for the moment.
      Tested with "make check" and the Ada ACATS testsuite.
      
      llvm-svn: 48640
      d97eea37
  2. Mar 20, 2008
  3. Mar 19, 2008
    • Christopher Lamb's avatar
      Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes... · 8fe91094
      Christopher Lamb authored
      Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491.
      
      llvm-svn: 48542
      8fe91094
    • Evan Cheng's avatar
      Fixed a coalescer bug caused by a typo. · 56e9e57d
      Evan Cheng authored
      llvm-svn: 48526
      56e9e57d
    • Evan Cheng's avatar
      Fix live variables issues: · 44c0b4f7
      Evan Cheng authored
      1. If part of a register is re-defined, an implicit kill and an implicit def are added to denote read / mod / write. However, this should only be necessary if the register is actually read later. This is a performance issue.
      2. If a sub-register is being defined, and it doesn't have a previous use, do not add a implicit kill to the last use of a super-register:
         = EAX, AX<imp-use,kill>
      ...
      AX =
      In this case, EAX is live but AX is killed, this is wrong and will cause the coalescer to do bad things.
      
      llvm-svn: 48521
      44c0b4f7
  4. Mar 18, 2008
  5. Mar 17, 2008
  6. Mar 16, 2008
  7. Mar 15, 2008
  8. Mar 14, 2008
  9. Mar 13, 2008
  10. Mar 12, 2008
    • Evan Cheng's avatar
      Experimental scheduler change to schedule / coalesce the copies added for... · 65e9d5f1
      Evan Cheng authored
      Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted:
      
      entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
      Live Ins: %EAX %EDX %ECX
              %reg1031<def> = MOVPC32r 0
              %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
              %reg1028<def> = MOV32rr %EAX
              %reg1029<def> = MOV32rr %EDX
              %reg1030<def> = MOV32rr %ECX
              %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
              %reg1025<def> = MOV32rr %reg1029
              %reg1026<def> = MOV32rr %reg1030
              %reg1024<def> = MOV32rr %reg1028
      
      The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.
      
      With -schedule-livein-copies:
      entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
      Live Ins: %EAX %EDX %ECX
              %reg1031<def> = MOVPC32r 0
              %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
              %reg1024<def> = MOV32rr %EAX
              %reg1025<def> = MOV32rr %EDX
              %reg1026<def> = MOV32rr %ECX
              %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]
      
      Much better!
      
      llvm-svn: 48307
      65e9d5f1
    • Duncan Sands's avatar
      Initial soft-float support for LegalizeTypes. I rewrote · 723849a1
      Duncan Sands authored
      the fcopysign expansion from LegalizeDAG to get rid of
      what seems to be a bug: the use of sign extension means
      that when copying the sign bit from an f32 to an f64,
      the upper 32 bits of the f64 (now an i64) are set, not
      just the top bit...  I also generalized it to work for
      any sized floating point types, and removed the bogosity:
        SDOperand Mask1 = (SrcVT == MVT::f64)
          ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
          : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
        Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
      (here SrcNVT is an integer with the same size as SrcVT).
      As far as I can see this takes a 1 << 63, converts to
      a double, converts that to a floating point constant
      then converts that to an integer constant, ending up
      with... 1 << 63 as an integer constant!  So I just
      generate this integer constant directly.
      
      llvm-svn: 48305
      723849a1
    • Dan Gohman's avatar
      Change VirtRegMap's dump to dump to cerr, not DOUT, so that it · 34ae72c4
      Dan Gohman authored
      can be called from within a debuger without having -debug specified
      on the command-line.
      
      llvm-svn: 48298
      34ae72c4
    • Dan Gohman's avatar
      Fix typos in comments. · bf68f9fd
      Dan Gohman authored
      llvm-svn: 48297
      bf68f9fd
    • Duncan Sands's avatar
      Fix typo. · c54fe97f
      Duncan Sands authored
      llvm-svn: 48295
      c54fe97f
    • Duncan Sands's avatar
      Don't try to extract an i32 from an f64. This · 87de65fc
      Duncan Sands authored
      getCopyToParts problem was noticed by the new
      LegalizeTypes infrastructure.  In order to avoid
      this kind of thing in the future I've added a
      check that EXTRACT_ELEMENT is only used with
      integers.  Once LegalizeTypes is up and running
      most likely BUILD_PAIR and EXTRACT_ELEMENT can
      be removed, in favour of using apints instead.
      
      llvm-svn: 48294
      87de65fc
    • Evan Cheng's avatar
      Clean up my own mess. · 99ee78ef
      Evan Cheng authored
      X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.
      
      llvm-svn: 48279
      99ee78ef
    • Owen Anderson's avatar
    • Owen Anderson's avatar
      When we're determining what registers to coallesce, track the VNInfo IDs for the definitions that · 70aaab6d
      Owen Anderson authored
      feed the PHI instructions.  We'll need these IDs in order to update LiveIntervals properly.
      
      llvm-svn: 48277
      70aaab6d
    • Evan Cheng's avatar
      Total brain cramp. · 0903aef2
      Evan Cheng authored
      llvm-svn: 48274
      0903aef2
    • Evan Cheng's avatar
      Set NextMII after issuing a physical register spill. · 105cb398
      Evan Cheng authored
      llvm-svn: 48263
      105cb398
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