- Mar 21, 2008
-
-
Duncan Sands authored
flags. This is needed by the new legalize types infrastructure which wants to expand the 64 bit constants previously used to hold the flags on 32 bit machines. There are two functional changes: (1) in LowerArguments, if a parameter has the zext attribute set then that is marked in the flags; before it was being ignored; (2) PPC had some bogus code for handling two word arguments when using the ELF 32 ABI, which was hard to convert because of the bogusness. As suggested by the original author (Nicolas Geoffray), I've disabled it for the moment. Tested with "make check" and the Ada ACATS testsuite. llvm-svn: 48640
-
- Mar 20, 2008
-
-
Christopher Lamb authored
llvm-svn: 48580
-
Evan Cheng authored
llvm-svn: 48578
-
Chris Lattner authored
llvm-svn: 48577
-
- Mar 19, 2008
-
-
Christopher Lamb authored
Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491. llvm-svn: 48542
-
Evan Cheng authored
llvm-svn: 48526
-
Evan Cheng authored
1. If part of a register is re-defined, an implicit kill and an implicit def are added to denote read / mod / write. However, this should only be necessary if the register is actually read later. This is a performance issue. 2. If a sub-register is being defined, and it doesn't have a previous use, do not add a implicit kill to the last use of a super-register: = EAX, AX<imp-use,kill> ... AX = In this case, EAX is live but AX is killed, this is wrong and will cause the coalescer to do bad things. llvm-svn: 48521
-
- Mar 18, 2008
-
-
Bill Wendling authored
llvm-svn: 48510
-
Dale Johannesen authored
llvm-svn: 48493
-
Christopher Lamb authored
Target independent DAG transform to use truncate for field extraction + sign extend on targets where this is profitable. Passes nightly on x86-64. llvm-svn: 48491
-
Evan Cheng authored
Rewrite code that propagate isDead information after a dead copy is coalesced. This remove some ugly spaghetti code and fixed a number of subtle bugs. llvm-svn: 48490
-
- Mar 17, 2008
-
-
Owen Anderson authored
the coalescer. This doesn't really work, but gets us farther than before. llvm-svn: 48446
-
- Mar 16, 2008
-
-
Christopher Lamb authored
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. llvm-svn: 48412
-
- Mar 15, 2008
-
-
Evan Cheng authored
llvm-svn: 48381
-
Evan Cheng authored
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
-
- Mar 14, 2008
-
-
Duncan Sands authored
table for nounwind calls. llvm-svn: 48373
-
Evan Cheng authored
Fix PR2138. Apparently any modification to a std::multimap (including remove entries for a different key) can invalidate multimap iterators. llvm-svn: 48371
-
Duncan Sands authored
llvm-svn: 48355
-
Nate Begeman authored
Use getIntPtrConstant in a couple places to shorten stuff up Handle splitting vector shuffles with undefs in the mask llvm-svn: 48351
-
Evan Cheng authored
Livein copy scheduling fixes: do not coalesce physical register copies, correctly determine the safe location to insert the copies. llvm-svn: 48348
-
- Mar 13, 2008
-
-
Dan Gohman authored
llvm-svn: 48344
-
Evan Cheng authored
llvm-svn: 48341
-
Evan Cheng authored
llvm-svn: 48337
-
Evan Cheng authored
Don't try to sink 3-address instruction if convertToThreeAddress created more than one instructions. llvm-svn: 48336
-
Evan Cheng authored
llvm-svn: 48334
-
Evan Cheng authored
TwoAddressInstructionPass enhancement. After it converts a two address instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one. llvm-svn: 48333
-
Christopher Lamb authored
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes. llvm-svn: 48329
-
Evan Cheng authored
llvm-svn: 48319
-
Evan Cheng authored
llvm-svn: 48311
-
- Mar 12, 2008
-
-
Evan Cheng authored
Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0: Live Ins: %EAX %EDX %ECX %reg1031<def> = MOVPC32r 0 %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def> %reg1028<def> = MOV32rr %EAX %reg1029<def> = MOV32rr %EDX %reg1030<def> = MOV32rr %ECX %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0] %reg1025<def> = MOV32rr %reg1029 %reg1026<def> = MOV32rr %reg1030 %reg1024<def> = MOV32rr %reg1028 The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled. With -schedule-livein-copies: entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0: Live Ins: %EAX %EDX %ECX %reg1031<def> = MOVPC32r 0 %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def> %reg1024<def> = MOV32rr %EAX %reg1025<def> = MOV32rr %EDX %reg1026<def> = MOV32rr %ECX %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0] Much better! llvm-svn: 48307
-
Duncan Sands authored
the fcopysign expansion from LegalizeDAG to get rid of what seems to be a bug: the use of sign extension means that when copying the sign bit from an f32 to an f64, the upper 32 bits of the f64 (now an i64) are set, not just the top bit... I also generalized it to work for any sized floating point types, and removed the bogosity: SDOperand Mask1 = (SrcVT == MVT::f64) ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); (here SrcNVT is an integer with the same size as SrcVT). As far as I can see this takes a 1 << 63, converts to a double, converts that to a floating point constant then converts that to an integer constant, ending up with... 1 << 63 as an integer constant! So I just generate this integer constant directly. llvm-svn: 48305
-
Dan Gohman authored
can be called from within a debuger without having -debug specified on the command-line. llvm-svn: 48298
-
Dan Gohman authored
llvm-svn: 48297
-
Duncan Sands authored
llvm-svn: 48295
-
Duncan Sands authored
getCopyToParts problem was noticed by the new LegalizeTypes infrastructure. In order to avoid this kind of thing in the future I've added a check that EXTRACT_ELEMENT is only used with integers. Once LegalizeTypes is up and running most likely BUILD_PAIR and EXTRACT_ELEMENT can be removed, in favour of using apints instead. llvm-svn: 48294
-
Evan Cheng authored
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases. llvm-svn: 48279
-
Owen Anderson authored
llvm-svn: 48278
-
Owen Anderson authored
feed the PHI instructions. We'll need these IDs in order to update LiveIntervals properly. llvm-svn: 48277
-
Evan Cheng authored
llvm-svn: 48274
-
Evan Cheng authored
llvm-svn: 48263
-