- Oct 17, 2008
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Daniel Dunbar authored
llvm-svn: 57716
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Chris Lattner authored
llvm-svn: 57715
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Bill Wendling authored
have an unreachable block in a function. This was triggering the assert. This is a horrid hack to cover this up. Oh! for a good debug info architecture! llvm-svn: 57714
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Mon P Wang authored
touches memory and need an associated MemOperand llvm-svn: 57712
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Dan Gohman authored
ISD condition opcodes into helper functions. llvm-svn: 57710
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Chris Lattner authored
llvm-svn: 57709
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Chris Lattner authored
in 32-bit mode instead of assigning a register pair. This has nothing to do with PR2356, but I happened to notice it while working on it. llvm-svn: 57704
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Chris Lattner authored
that have different sizes (e.g. i32 and i64) make sure to reserve registers for the bigger operand. llvm-svn: 57699
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Mon P Wang authored
llvm-svn: 57696
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Chris Lattner authored
llvm-svn: 57695
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Chris Lattner authored
other than why it was xfailed. llvm-svn: 57694
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Ted Kremenek authored
"Implement" GRExprEngine::VisitLValue for ObjCPropertyRefExpr. This is only a bandid; we need to properly handle properties by using locv/nonloc objects and specially handling property assignments in the transfer function for BinaryOperator. llvm-svn: 57693
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Evan Cheng authored
Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions except they do not have any operands. The RegModRM byte is encoded with register number 0. llvm-svn: 57692
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Evan Cheng authored
llvm-svn: 57691
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Chris Lattner authored
llvm-svn: 57690
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Chris Lattner authored
constraint. Reject asms where an output has multiple input constraints tied to it. llvm-svn: 57687
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Chris Lattner authored
array. Improve some minor comments, refactor some helpers in AsmOperandInfo. No functionality change for valid code. llvm-svn: 57686
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Daniel Dunbar authored
- Encode unions and bit-fields correctly. - Accept option to name record fields (used for NeXT runtime). llvm-svn: 57685
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Daniel Dunbar authored
simplifies clients. Also, add assert that RegionStack is empty when the CGDebugInfo is destroyed. llvm-svn: 57684
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Daniel Dunbar authored
llvm-svn: 57683
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Gabor Greif authored
llvm-svn: 57677
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Gabor Greif authored
distinguished from normal (untagged) ones as per review comment. I am sufficiently unaquainted with doxygen to defer the markup to someone with more experience. llvm-svn: 57676
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Daniel Dunbar authored
- Mechanism for detecting if a structure should be expanded wasn't reliable. Simplified by just keeping track of what we should be expanding. - This fixes a bug in using NSInvocation to invoke a method which returned a structure, which in used by Key Value Observing, which in the end, caused a miscompile in poor little Sketch. llvm-svn: 57675
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Daniel Dunbar authored
llvm-svn: 57674
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Evan Cheng authored
llvm-svn: 57673
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Chris Lattner authored
should work for intel long double, but ppc long double aborts in convert. llvm-svn: 57672
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Zhongxing Xu authored
RVal => SVal LVal => Loc NonLVal => NonLoc lval => loc nonlval => nonloc llvm-svn: 57671
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Zhongxing Xu authored
llvm-svn: 57670
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Dan Gohman authored
constants that don't fit in an int. This fixes "this decimal constant is unsigned only in ISO C90" warnings. llvm-svn: 57668
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Daniel Dunbar authored
floating point. This is only correct for x86-32 at the moment. llvm-svn: 57667
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Zhongxing Xu authored
llvm-svn: 57666
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Zhongxing Xu authored
type T. llvm-svn: 57665
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Zhongxing Xu authored
struct s {}; void f() { int a[10]; int (*p)[10]; p = &a; (*p)[3] =1; struct s d; struct s *q; q = &d; } We return the corresponding MemRegionVal for them. llvm-svn: 57664
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Dan Gohman authored
use a SUB instruction instead of an ADD, because -128 can be encoded in an 8-bit signed immediate field, while +128 can't be. This avoids the need for a 32-bit immediate field in this case. A similar optimization applies to 64-bit adds with 0x80000000, with the 32-bit signed immediate field. To support this, teach tablegen how to handle 64-bit constants. llvm-svn: 57663
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Dan Gohman authored
shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. llvm-svn: 57662
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Daniel Dunbar authored
structure. - I'm not sure yet about the behavior, but this at least prevents the crash. Add some asserts on RegionStack usage. llvm-svn: 57661
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Dan Gohman authored
llvm-svn: 57660
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Ted Kremenek authored
llvm-svn: 57659
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Ted Kremenek authored
llvm-svn: 57658
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Ted Kremenek authored
Remove GRExprEngine::getLVal and RValues::MakeVal. Enhance StoreManager "GetLValue" methods to dispatch for specific kinds of lvalue queries, as opposed to interogating the expression tree (GRExprEngine already does this). Added FIXMEs. In particular, we no longer "assume" that a base pointer in a field/array access is null (this logic was removed). Perhaps we should do this when fetching the lvalue for fields and array elements? llvm-svn: 57657
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