CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags. 

This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.

llvm-svn: 49123

when some another register is used for argument passing.
Currently is used on Win64.

llvm-svn: 49079

start of a filename, not a filename+length.  All clients can produce a
null terminated name, and the system api's require null terminated 
strings anyway.

llvm-svn: 49041

llvm-svn: 48907

llvm-svn: 48874

llvm-svn: 48801

marked read-write. Use const so that they can be allocated in a
read-only segment.

llvm-svn: 48800

on ideas mentioned in PR686.
Written by Mikhail Glushenkov and contributed by Codedgers, Inc.

Old llvmc will be removed soon after new one will have all its properties.

llvm-svn: 48699

llvm-svn: 48696

flags.  This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines.  There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness.  As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.

llvm-svn: 48640

llvm-svn: 48577

llvm-svn: 48450

Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.

llvm-svn: 48412

llvm-svn: 48381

Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

llvm-svn: 48380

Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 

Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329

llvm-svn: 48222

llvm-svn: 48200

llvm-svn: 48167

Patch by Joachim Durchholz. Thanks!

llvm-svn: 48139

llvm-svn: 48126

Add support in TableGen for unknown operands that infer their type from the pattern their used in. This will be used to allow insert/extract subreg patterns in .td files!

llvm-svn: 48125

field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff.  Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and 
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)

llvm-svn: 48122

were being pruned in patterns where a variable was used more than once, e.g.:

  (or (and R32C:$rA, R32C:$rC), (and R32C:$rB, (not R32C:$rC)))

In this example, $rC is used more than once and is actually significant to
instruction selection pattern matching when commuted variants are produced.
This patch scans the pattern's clauses and collects the variables, creating
a set of variables that are used more than once. TreePatternNode::isIsomorphicTo()
also understands that multiply-used variables are significant.

llvm-svn: 47950

llvm-svn: 47763

llvm-svn: 47761

llvm-svn: 47629

would have been a Godsend here!

llvm-svn: 47625

llvm-svn: 47595

%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.

llvm-svn: 47534

llvm-svn: 47367

tblgen will complain if a sign-extended constant does not fit into a
data type smaller than i32, e.g., i16. This causes a problem when certain
hex constants are used, such as 0xff for byte masks or immediate xor
values.

tblgen will try the sign-extended value first and, if the sign extended
value would overflow, it tries to see if the unsigned value will fit.
Consequently, a software developer can now safely incant:

	(XORHIr16 R16C:$rA, 0xffff)

which is somewhat clearer and more informative than incanting:

	(XORHIr16 R16C:$rA, (i16 -1))

even if the two are bitwise equivalent.

Tblgen also outputs the 64-bit unsigned constant in the generated ISel code
when getTargetConstant() is invoked.

llvm-svn: 47188

it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to.  Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.

llvm-svn: 47143

1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
   if it is legal.

This allows ConstantFP to be handled like Constant, allowing for 
targets that can encode FP immediates as MachineOperands.

As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants!  Hooray.

llvm-svn: 47121

llvm-svn: 47012

llvm-svn: 46930

llvm-svn: 46901

initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.

llvm-svn: 46827

llvm-svn: 46776

Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.

llvm-svn: 46724