llvm-svn: 11449

llvm-svn: 11430

std::numeric_limits<float>::max() for weighting preallocated
intervals.

llvm-svn: 11427

llvm-svn: 11393

Whitespace cleanups.

llvm-svn: 11389

Add MachineBasicBlock::dump().

llvm-svn: 11364

Rename SetMachineOperandConst's formal parameters to match other methods here.
Mark some methods as being used only by the SPARC back-end.
Fix a missing-paren bug in OutputValue().

llvm-svn: 11363

MachineBasicBlock. Also change opcode to a short and numImplicitRefs
to an unsigned char so that overall MachineInstr's size stays the
same.

llvm-svn: 11357

llvm-svn: 11348

llvm-svn: 11346

ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.

llvm-svn: 11340

llvm-svn: 11339

llvm-svn: 11285

llvm-svn: 11283

llvm-svn: 11278

llvm-svn: 11239

instead of randomly groping about inside its outEdges array.
Make SchedGraph::addDummyEdges() use getNumOutEdges() instead of
outEdges.size().
Get rid of ifdefed-out code in SchedGraph::buildGraph().

llvm-svn: 11238

the Virt2PhysRegMap std::map with an std::vector.  This speeds up the
register allocator another (almost) 40%, from .72->.45s in a release build
of LLC on 253.perlbmk.

llvm-svn: 11219

speeds up livevar from .48/.32s -> .45/.31s in LLC on perlbmk

llvm-svn: 11217

This speeds up live variables a lot, from .60/.39s -> .47/.26s in LLC, for
the first/second pass respectively.

llvm-svn: 11216

from physical registers, and they are always dense, it makes sense to not have
a ton of RBtree overhead.  This change speeds up regalloclocal about ~30% on
253.perlbmk, from .35s -> .27s in the JIT (in LLC, it goes from .74 -> .55).

Now live variable analysis is the slowest codegen pass.  Of course it doesn't
help that we have to run it twice, because regalloclocal doesn't update it,
but even if it did it would be the slowest pass (now it's just the 2x slowest
pass :(

llvm-svn: 11215

llvm-svn: 11151

of the virtual register to certain functions.

llvm-svn: 11143

slots each. As a concequence they get numbered as 0, 2, 4 and so
on. The first slot is used for operand uses and the second for
defs. Here's an example:

0: A = ...
2: B = ...
4: C = A + B ;; last use of A

The live intervals should look like:

A = [1, 5)
B = [3, x)
C = [5, y)

llvm-svn: 11141

access. Rather we only have to do it on the creation of the interval.

llvm-svn: 11135

llvm-svn: 11129

operand of the instruction and thus simplify the register allocation.

llvm-svn: 11124

spilled, A was loaded from its stack location twice. This fixes the bug.

llvm-svn: 11093

llvm-svn: 11091

llvm-svn: 11088

llvm-svn: 11087

outside of loops = 0.

llvm-svn: 11085

much better when I get rid of the reserved registers.

llvm-svn: 11066

registers (not as the max number of registers).

Change toSpill from a std::set into a std::vector<bool>.

Use the reverse iterator adapter to do a reverse scan of allocatable
registers.

llvm-svn: 11061

where appropriate.

llvm-svn: 11060

llvm-svn: 11057

llvm-svn: 11054

llvm-svn: 11050

llvm-svn: 11048

llvm-svn: 11047