entend flag.

llvm-svn: 150774

llvm-svn: 150773

llvm-svn: 150771

Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786.

llvm-svn: 150769

llvm-svn: 150768

llvm-svn: 150739

llvm-svn: 150737

processor, due to the Atom scheduler producing an instruction sequence that is
different from that which is expected.
Patch by Michael Spencer!

llvm-svn: 150736

llvm-svn: 150715

llvm-svn: 150712

Call clobbers are now represented with register mask operands.  The
regmask can easily represent the fact that xmm6 is call-preserved while
ymm6 isn't.  This is automatically computed by TableGen from the
CalleeSavedRegs containing xmm6.

llvm-svn: 150709

The different calling conventions and call-preserved registers are
represented with regmask operands that are added dynamically.

llvm-svn: 150708

llvm-svn: 150706

Disable machine copy propagation for now. It's known to be buggy (PR11940) and introduces subtle miscompiles in many places.

llvm-svn: 150703

Turns out this isn't safe, because the code below depends on LHS and RHS having
the same type.

llvm-svn: 150695

llvm-svn: 150694

llvm-svn: 150690

llvm-svn: 150679

llvm-svn: 150678

llvm-svn: 150677

llvm-svn: 150670

Modify the algorithm when traversing the DAGCombiner's worklist to be O(log N) for all operations. This fixes a horrible worst case with lots of nodes where 99% of the time was being spent in std::remove.

llvm-svn: 150669

With MSVCRT, prior checker missed emission of #INF and #NAN.

FIXME: Checking should be simpler.
llvm-svn: 150667

Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.

Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.

llvm-svn: 150664

Template specialize SmallVector::push_back based on POD-ness of the type.  Reduces clang binary by 188KB

llvm-svn: 150662

atof(3) might behave differently among platforms.

llvm-svn: 150661

llvm-svn: 150655

llvm-svn: 150654

llvm-svn: 150653

The rule governing the flags is this:

  no-gc + no-gc   = no-gc
  no-gc +    gc   = no-gc
  no-gc + gc-only = error
     gc +    gc   = gc
     gc + gc-only = gc-only
gc-only + gc-only = gc-only

llvm-svn: 150646

loop-rotate shouldn't hoist alloca instructions out of a loop.  Patch by Patrik Hägglund, with slightly modified test.  Issue reported by Patrik Hägglund on llvmdev.

llvm-svn: 150642

Call instructions no longer have a list of 43 call-clobbered registers.
Instead, they get a single register mask operand with a bit vector of
call-preserved registers.

This saves a lot of memory, 42 x 32 bytes = 1344 bytes per call
instruction, and it speeds up building call instructions because those
43 imp-def operands no longer need to be added to use-def lists. (And
removed and shifted and re-added for every explicit call operand).

Passes like LiveVariables, LiveIntervals, RAGreedy, PEI, and
BranchFolding are significantly faster because they can deal with call
clobbers in bulk.

Overall, clang -O2 is between 0% and 8% faster, uniformly distributed
depending on call density in the compiled code.  Debug builds using
clang -O0 are 0% - 3% faster.

I have verified that this patch doesn't change the assembly generated
for the LLVM nightly test suite when building with -disable-copyprop
and -disable-branch-fold.

Branch folding behaves slightly differently in a few cases because call
instructions have different hash values now.

Copy propagation flushes its data structures when it crosses a register
mask operand. This causes it to leave a few dead copies behind, on the
order of 20 instruction across the entire nightly test suite, including
SPEC. Fixing this properly would require the pass to use different data
structures.

llvm-svn: 150638

llvm-svn: 150636

llvm-svn: 150635

Don't attempt to move instructions with regmask operands. They are most
likely calls anyway.

llvm-svn: 150634

The existing framework for postra scheduling is library local. We want to keep it that way. Soon we will have a more general MachineScheduler interface. At that time, various bits will be exposed to targets. In the meantime, the VLIWPacketizer wants to use ScheduleDAGInstrs directly, so it needs to wrapped in a PIMPL to avoid exposing it to the target interface.

llvm-svn: 150633

llvm-svn: 150632

llvm-svn: 150630

llvm-svn: 150628

llvm-svn: 150627