Commits · fd2adbfa280d065b96d6a0819ddd4abaa9b91de9 · Roger Ferrer / llvm-epi-0.8

Nov 06, 2008
- Encode pic load / store instructions; fix some encoding bugs. · fd2adbfa
  Evan Cheng authored Nov 05, 2008
  
  llvm-svn: 58780
  fd2adbfa
Nov 05, 2008

Restructure ARM code emitter to use instruction formats instead of addressing... · 81889d01

Evan Cheng authored Nov 05, 2008

Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.

llvm-svn: 58764

81889d01

Nov 04, 2008
- LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR. · 453844c3
  Evan Cheng authored Nov 04, 2008
  
  llvm-svn: 58707
  453844c3
Nov 03, 2008
- Add binary encoding support for multiply instructions. Some blanks left to... · 4d0549e3
  Jim Grosbach authored Nov 03, 2008
  
  Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there. llvm-svn: 58626
  4d0549e3
Oct 14, 2008
- Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) · b7c01f5f
  Jim Grosbach authored Oct 14, 2008
  
  llvm-svn: 57524
  b7c01f5f
Sep 17, 2008
- Fix addrmode1 instruction encodings; fix bx_ret encoding. · 7848cfcd
  Evan Cheng authored Sep 17, 2008
  
  llvm-svn: 56277
  7848cfcd
- Specify instruction encoding using range list to avoid endianess issues. · 937569af
  Evan Cheng authored Sep 17, 2008
  
  llvm-svn: 56276
  937569af
Sep 13, 2008
- Revert 56176. All those instruction formats are still needed. · 12134701
  Evan Cheng authored Sep 13, 2008
  
  llvm-svn: 56180
  12134701
- Eliminate unnecessary instruction formats. · c5c74f36
  Evan Cheng authored Sep 12, 2008
  
  llvm-svn: 56176
  c5c74f36
- Addrmode 1 S bit can be dynamically set. Look for CPSR def. · d1424c4e
  Evan Cheng authored Sep 12, 2008
  
  llvm-svn: 56172
  d1424c4e
Sep 01, 2008
- Control flow instruction encodings. · fa558788
  Evan Cheng authored Sep 01, 2008
  
  llvm-svn: 55601
  fa558788
- ldm / stm instruction encodings. · c288cc05
  Evan Cheng authored Sep 01, 2008
  
  llvm-svn: 55599
  c288cc05
- AXI2 and AXI3 instruction encodings. · c37532b2
  Evan Cheng authored Sep 01, 2008
  
  llvm-svn: 55598
  c37532b2
- Reorganize instruction formats again; AXI1 encoding. · a2827234
  Evan Cheng authored Sep 01, 2008
  
  llvm-svn: 55597
  a2827234
- addrmode3 instruction encodings. · 169eccc2
  Evan Cheng authored Sep 01, 2008
  
  llvm-svn: 55596
  169eccc2
- Reorganize some instruction format definitions. No functionality change. · 624844b4
  Evan Cheng authored Sep 01, 2008
  
  llvm-svn: 55594
  624844b4
- Rest of addrmode2 instruction encodings. · cccca875
  Evan Cheng authored Sep 01, 2008
  
  llvm-svn: 55593
  cccca875
Aug 31, 2008
- Addr2 word / byte load encodings. · 01fd3f12
  Evan Cheng authored Aug 31, 2008
  
  llvm-svn: 55591
  01fd3f12
- Addr1 instructions opcodes are encoded in bits 21-24; encode S bit. · 5b6c931e
  Evan Cheng authored Aug 31, 2008
  
  llvm-svn: 55590
  5b6c931e
Aug 29, 2008
- addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode. · c139c221
  Evan Cheng authored Aug 29, 2008
  
  llvm-svn: 55531
  c139c221
- More refactoring. · ee98fa9d
  Evan Cheng authored Aug 29, 2008
  
  llvm-svn: 55528
  ee98fa9d
- Refactor ARM instruction format definitions into a separate file. No functionality changes. · 2d37f19e
  Evan Cheng authored Aug 28, 2008
  
  llvm-svn: 55518
  2d37f19e