When using register masks, registers like %rip are clobbered by the
register mask. LICM should still be able to hoist instructions reading
%rip from a loop containing calls.

llvm-svn: 150288

llvm-svn: 150286

Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

llvm-svn: 150100

llvm-svn: 150099

llvm-svn: 150098

It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

llvm-svn: 149646

This fixes a typo in r148589.

llvm-svn: 148724

llvm-svn: 148723

Only PostRA LICM is affected.

llvm-svn: 148589

It is safe to move uses of such registers.

llvm-svn: 148259

llvm-svn: 147884

llvm-svn: 147127

Fixes <rdar://problem/10584116>

llvm-svn: 147125

generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026

1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975

llvm-svn: 144747

Disable LICM speculation in high register pressure situation again now that Devang has fixed other issues.

llvm-svn: 143003

llvm-svn: 142593

llvm-svn: 142592

llvm-svn: 142234

Radar 10281206.

llvm-svn: 142202

llvm-svn: 141844

Disable machine LICM speculation check (for profitability) until I have time to investigate the regressions.

llvm-svn: 141813

containing loop's header to see if that's a landing pad. If it is, then we don't
want to hoist instructions out of the loop and above the header.

llvm-svn: 141767

1. The speculation check may not have been performed if the BB hasn't had a load
   LICM candidate.
2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the
   instruction even if it's in high register pressure situation.

llvm-svn: 141747

Also teach MachineLICM to avoid "speculation" when register pressure is high.

llvm-svn: 141744

The blocks with invokes have branches to the dispatch block, because that more
correctly models the behavior of the CFG. The dispatch of course has edges to
the landing pads. Those landing pads could contain invokes, which then have
branches back to the dispatch. This creates a loop. The machine LICM pass looks
at this loop and thinks it can hoist elements out of it. But because the
dispatch is an alternate entry point into the program, the hoisted instructions
won't be executed.

I wasn't able to get a testcase which was small and could reproduce all of the
time. The function_try_block.cpp in llvm-test was where this showed up.

llvm-svn: 141726

For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141689

llvm-svn: 141594

llvm-svn: 141576

For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141569

Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690

llvm-svn: 138934

llvm-svn: 134049

sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021

llvm-svn: 133944

Look pass copies when determining whether hoisting would end up inserting more copies. rdar://9266679

llvm-svn: 129297

llvm-svn: 127175

TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.

llvm-svn: 123905

These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 123155

llvm-svn: 118803