Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0.

llvm-svn: 35138

llvm-svn: 35137

llvm-svn: 35135

to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

llvm-svn: 35134

llvm-svn: 35133

in that BB.

llvm-svn: 35132

llvm-svn: 35129

Fix MultiSource/Applications/aha test.

llvm-svn: 35128

llvm-svn: 35127

llvm-svn: 35126

llvm-svn: 35125

computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

llvm-svn: 35123

llvm-svn: 35122

folded into target addressing mode for the given type.

llvm-svn: 35121

Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.

llvm-svn: 35119

llvm-svn: 35118

llvm-svn: 35117

it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.

llvm-svn: 35109

llvm-svn: 35108

llvm-svn: 35107

llvm-svn: 35105

llvm-svn: 35104

llvm-svn: 35097

llvm-svn: 35096

llvm-svn: 35095

llvm-svn: 35094

llvm-svn: 35093

e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.

llvm-svn: 35089

llvm-svn: 35088

llvm-svn: 35087

llvm-svn: 35086

llvm-svn: 35083

Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll

llvm-svn: 35082

"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().

llvm-svn: 35080

  1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
  2. Make code more efficient.

llvm-svn: 35078

llvm-svn: 35077

More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.

llvm-svn: 35076

llvm-svn: 35075

More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.

llvm-svn: 35074

 a legal target address immediate or scale.

llvm-svn: 35073