llvm-svn: 79318

llvm-svn: 78970

llvm-svn: 78918

llvm-svn: 78908

llvm-svn: 78905

llvm-svn: 78904

Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.

llvm-svn: 78827

llvm-svn: 78806

llvm-svn: 78777

llvm-svn: 78717

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

llvm-svn: 78701

llvm-svn: 78657

llvm-svn: 78610

llvm-svn: 78550

'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514

llvm-svn: 78410

It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.

This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361

Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.

llvm-svn: 78321

llvm-svn: 78126

Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.

llvm-svn: 78030

llvm-svn: 77781

llvm-svn: 77764

instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756

llvm-svn: 77743

llvm-svn: 77627

llvm-svn: 77625

llvm-svn: 77611

llvm-svn: 77507

- Darwin Thumb2 call clobbers r9.

llvm-svn: 77500

llvm-svn: 77422

In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).

llvm-svn: 77364

llvm-svn: 77363

llvm-svn: 77340

llvm-svn: 77329

- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300

llvm-svn: 77275

llvm-svn: 77201

llvm-svn: 77199

Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024