SCEVAddRecExpr doesn't necessarily dominate blocks merely dominated
by all of its operands. This fixes an abort compiling 403.gcc.

llvm-svn: 96056

llvm-svn: 96055

separate LLVMContexts.

llvm-svn: 96051

encoder and decoder by using new MRM_ forms.

llvm-svn: 96048

rip-relative addresses, and add a testcase.

llvm-svn: 96040

The solution there produces correct code, but is seriously
deficient in several ways.

llvm-svn: 96039

llvm-svn: 96038

Patch by Shivram K!

llvm-svn: 96037

addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036

Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.

llvm-svn: 96032

llvm-svn: 96031

llvm-svn: 96029

llvm-svn: 96028

is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026

Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.

llvm-svn: 96023

llvm-svn: 96020

llvm-svn: 96019

stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot.  Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.

SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.

Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.

llvm-svn: 96015

llvm-svn: 96011

llvm-svn: 96010

llvm-svn: 96008

llvm-svn: 96007

llvm-svn: 96006

llvm-svn: 96005

offset distributions it doesn't expect.

llvm-svn: 96002

llvm-svn: 95999

didn't handle
X =
Y<dead> = use X
DBG_VALUE(X)
I was hoping to avoid this approach as it's slower,
but I don't think it can be done.

llvm-svn: 95996

2. don't bother trying to merge globals in non-default sections,
   doing so is quite dubious at best anyway.
3. fix a bug reported by Arnaud de Grandmaison where we'd try to
   merge two globals in different address spaces.

llvm-svn: 95995

is breaking llvm-gcc bootstrap.

llvm-svn: 95988

llvm-svn: 95981

This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936

llvm-svn: 95980

doesn't matter, except that ScalarEvolution tends to need less time
to fold the results this way.

llvm-svn: 95979

bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.

This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.

llvm-svn: 95975

* Enabled R1/R2 application for nodes with infinite spill costs in the Briggs heuristic (made
safe by the changes to the normalization proceedure).
* Removed a redundant header.

llvm-svn: 95973

This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960

great solution for the disassembler, we'll go with "plan b".

llvm-svn: 95957

MRRC, MRRc2.  For disassembly only.

llvm-svn: 95955

reduce down to a single value.  InstCombine already does this transformation
but DAG legalization may introduce new opportunities.  This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized.  I measured the compile time 
impact of this (running llc on 176.gcc) and it was not significant.

llvm-svn: 95951

with "tied memory operands", which is wrong.

llvm-svn: 95950

llvm-svn: 95949