This will be used to implement an optimisation for literal entries
in special case lists.

Differential Revision: http://llvm-reviews.chandlerc.com/D1278

llvm-svn: 187731

llvm-svn: 187730

Tracked by <rdar://problem/14648821>.

llvm-svn: 187729

SCoP invariant parameters with the different start value would deter parameter
sharing. For example, when compiling the following C code:

  void foo(float *input) {
    for (long j = 0; j < 8; j++) {
      // SCoP begin
      for (long i = 0; i < 8; i++) {
        float x = input[j * 64 + i + 1];
        input[j * 64 + i] = x * x;
      }
    }
  }

Polly would creat two parameters for these memory accesses:

    p_0: {0,+,256}
    p_2: {4,+,256}
    [j * 64 + i + 1] => MemRef_input[o0] : 4o0 = p_1 + 4i0
    [j * 64 + i]     => MemRef_input[o0] : 4o0 = p_0 + 4i0

These parameters only differ from start value. To enable parameter sharing,
we split the start value from SCEVAddRecExpr, so they would share a single
parameter that always has zero start value:

    p0: {0,+,256}<%for.cond1.preheader>
    [j * 64 + i + 1] => MemRef_input[o0] : 4o0 = 4 + p_1 + 4i0
    [j * 64 + i]     => MemRef_input[o0] : 4o0 = p_0 + 4i0

Such translation can make the polly-dependence much faster.

Contributed-by: Star Tan <tanmx_star@yeah.net>
llvm-svn: 187728

llvm-svn: 187727

llvm-svn: 187726

llvm-svn: 187725

LLVM Interpreter: This patch implements vector support for cast operations (zext, sext, uitofp, sitofp, trunc, fpext, fptosi, fptrunc, bitcast) and shift operations (shl, ashr, lshr) for integer and floating point data types.
Added tests.

Done by Yuri Veselov (mailto:Yuri.Veselov@intel.com).

llvm-svn: 187724

This patch just uses a peephole test for "add; compare; branch" sequences
within a single block.  The IR optimizers already convert loops to
decrement-and-branch-on-nonzero form in some cases, so even this
simplistic test triggers many times during a clang bootstrap and
projects/test-suite run.  It looks like there are still cases where we
need to more strongly prefer branches on nonzero though.  E.g. I saw a
case where a loop that started out with a check for 0 ended up with a
check for -1.  I'll try to look at that sometime.

I ended up adding the Reference class because MachineInstr::readsRegister()
doesn't check for subregisters (by design, as far as I could tell).

llvm-svn: 187723

llvm-svn: 187722

llvm-svn: 187721

llvm-svn: 187720

Just the definitions and MC support.  The next patch uses them for codegen.

llvm-svn: 187719

Perhaps predictably, doing comparison elimination on the fly during
SystemZLongBranch turned out to be a bad idea.  The next patches make
use of LOAD AND TEST and BRANCH ON COUNT, both of which require
changes to earlier instructions.

No functionality change intended.

llvm-svn: 187718

Added intrinsics and tests.

llvm-svn: 187717

Use a shuffle with undef elements instead of inserting 0s in the 128-bit to 256-bit casting intrinsics to improve performance. Thanks to Katya Romanova for identifying this issue.

llvm-svn: 187716

Sema::PerformObjectMemberConversion assumed that the Qualifier it was
given holds a type. However, the specifier could hold just a namespace.
In this case, we should ignore the qualifier and not attempt to cast to
it.

llvm-svn: 187715

llvm-svn: 187714

llvm-svn: 187713

helper functions. This can be optimized out later when the remaining
parts of the helper function work is moved into the Mips16HardFloat pass.
For now it forces us to use the 32 bit save/restore instructions instead
of the 16 bit ones.

llvm-svn: 187712

Note that this will require a recent version of the linker for Darwin
builds with LTO to pass these tests.

llvm-svn: 187711

Part of <rdar://problem/14620988>

llvm-svn: 187710

llvm-svn: 187709

Fixes shared cmake build.

llvm-svn: 187708

This addresses comments in post-commit review of r187345.

llvm-svn: 187707

double test(double a, double b, double c, double d) { return a<b ? c : d; }

before:
_test:
	ucomisd	%xmm0, %xmm1
	ja	LBB0_2
	movaps	%xmm3, %xmm2
LBB0_2:
	movaps	%xmm2, %xmm0

after:
_test:
	cmpltsd	%xmm1, %xmm0
	andpd	%xmm0, %xmm2
	andnpd	%xmm3, %xmm0
	orpd	%xmm2, %xmm0

Small speedup on Benchmarks/SmallPT

llvm-svn: 187706

llvm-svn: 187705

Apparently Atoms use lea for stack adjustment, which we weren't
looking for.

llvm-svn: 187704

Due to the weird and wondeful usual arithmetic conversions, some
calculations involving negative values were getting performed in
uint32_t and then promoted to int64_t, which is really not a good
idea.

Patch by Katsuhiro Ueno.

llvm-svn: 187703

llvm-svn: 187702

llvm-svn: 187701

Store them in a place that gets cleaned up properly.

llvm-svn: 187700

llvm-svn: 187699

llvm-svn: 187698

Dyld never outlives MemMgr, just put both on the stack.

llvm-svn: 187697

Using an object to do the cleanup may look like overkill, but it's safer and nicer than putting deletes everywhere.

llvm-svn: 187696

llvm-svn: 187695

Add support for passing -1 to __builtin_shufflevector to signify an undefined element value to match IR capabilities.

llvm-svn: 187694

Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the
64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with
explicit register names, on PPC64 when an i64 MVT has been requested, we need
to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent)
registers.

At some point, we'll probably want to arrange things so that the generic code
in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order
to match these inline asm register constraints. If we do that, this change can
be reverted.

llvm-svn: 187693

Remove assertion that the verifier should catch.

llvm-svn: 187692