llvm-svn: 133895

llvm-svn: 133886

llvm-svn: 133875

llvm-svn: 133874

The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is
not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support
boolean values.

llvm-svn: 133873

llvm-svn: 133872

llvm-svn: 133871

llvm-svn: 133870

llvm-svn: 133869

llvm-svn: 133868

pointing to the range [first character, last character] instead of just not
after the last character. Patch by Yan Ivnitskiy!

llvm-svn: 133867

llvm-svn: 133863

llvm-svn: 133859

<rdar://problem/9483883>

llvm-svn: 133858

Hopefully make the x86-target-only Windows bots happy.

llvm-svn: 133856

llvm-svn: 133853

llvm-svn: 133851

llvm-svn: 133847

llvm-svn: 133846

llvm-svn: 133845

Move the target-specific RecordRelocation logic out of the generic MC
MachObjectWriter and into the target-specific object writers. This allows
nuking quite a bit of target knowledge from the supposedly target-independent
bits in lib/MC.

llvm-svn: 133844

The scheduler needs to be aware on the existence of untyped nodes when it performs type propagation for EXTRACT_SUBREG.

llvm-svn: 133838

Sorry, this was a bad idea.  Within clang these builtins are in a separate
"ARM" namespace, but the actual builtin names should clearly distinguish that
they are target specific.

llvm-svn: 133832

llvm-svn: 133830

llvm-svn: 133828

llvm-svn: 133825

overheads.  No functional change intended.

llvm-svn: 133824

llvm-svn: 133823

llvm-svn: 133822

llvm-svn: 133821

- Rename TargetRegisterDesc to MCRegisterDesc.

llvm-svn: 133820

The fixup value comes in as the whole 32-bit value, so for the lo16 fixup,
the upper bits need to be masked off. Previously we assumed the masking had
already been done and asserted.

rdar://9635991

llvm-svn: 133818

llvm-svn: 133815

The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates.

llvm-svn: 133814

instructions can be used to match combinations of multiply/divide and VCVT 
(between floating-point and integer, Advanced SIMD).  Basically the VCVT 
immediate operand that specifies the number of fraction bits corresponds to a 
floating-point multiply or divide by the corresponding power of 2.

For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a 
combination of VMUL and VCVT (floating-point to integer) as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vmul.f32        d16, d17, d16
  vcvt.s32.f32    d16, d16
becomes:
  vcvt.s32.f32    d16, d16, #3

Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a 
combinations of VCVT (integer to floating-point) and VDIV as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vcvt.f32.s32    d16, d16
  vdiv.f32        d16, d17, d16
becomes:
  vcvt.f32.s32    d16, d16, #3

llvm-svn: 133813

     .file and .loc directives.

Ideally, we would utilize the existing support in AsmPrinter for this, but
I cannot find a way to get .file and .loc directives to print without the
rest of the associated DWARF sections, which ptxas cannot handle.

llvm-svn: 133812

 enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811

rdar://9667872

llvm-svn: 133808

static variables or functions. 

llvm-svn: 133803

     targets: g80, gt200, gf100(fermi)

llvm-svn: 133799