llvm-svn: 28848

magic to work.

llvm-svn: 28847

llvm-svn: 28846

llvm-svn: 28843

llvm-svn: 28841

llvm-svn: 28840

now compile:

static unsigned long X;
void test1() {
  X = 0;
}

into:

_test1:
        lis r2, ha16(_X)
        li r3, 0
        stw r3, lo16(_X)(r2)
        blr

Totally amazing :)

llvm-svn: 28839

llvm-svn: 28838

llvm-svn: 28837

the target triple & subtarget info.  woo.

llvm-svn: 28835

llvm-svn: 28834

llvm-svn: 28832

Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.

llvm-svn: 28830

add a new init method.

llvm-svn: 28828

llvm-svn: 28827

llvm-svn: 28826

support, and 64-bit register use are all consistent with each other.

Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently.  This not makes ppc64 blow up on lots
of stuff :)

llvm-svn: 28825

can in 32-bit mode we can choose to optionally *use* 64-bit registers.

llvm-svn: 28824

llvm-svn: 28819

llvm-svn: 28818

2. Update docs for vector debug support and new version control.

3. Simplify serialization of DebugDescInfo subclasses.

llvm-svn: 28816

printf("%s\n", str) -> puts(str)
printf("%c", c) -> putchar(c)
Also fixed fprintf(file, "%c", c) -> fputc(c, file)

llvm-svn: 28815

llvm-svn: 28814

that is currently just like ppc32 :)

llvm-svn: 28813

llvm-svn: 28812

the Signals module that registered the handlers would cause the stack trace
to be generated. Now, you must explicitly call PrintStackTraceOnErrorSignal
in order for that to happen.

llvm-svn: 28810

live at function entry.  This prevents it from using arg registers for other
purposes before the arguments are used.

llvm-svn: 28809

llvm-svn: 28808

2. Add vector support.

llvm-svn: 28807

thing.  Doubles still need to be special cased.

llvm-svn: 28806

idioms into bswap intrinsics.

llvm-svn: 28803

to get the alignment of the element type.

llvm-svn: 28799

llvm-svn: 28798

llvm-svn: 28797

llvm-svn: 28796

llvm-svn: 28795

llvm-svn: 28794

operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791

vector types are passed via XMM registers.

llvm-svn: 28789

llvm-svn: 28787