Skip to content
Commit 0a656498 authored by Matt Arsenault's avatar Matt Arsenault
Browse files

AMDGPU: Combine directly on mul24 intrinsics

The problem these are supposed to work around can occur before the
intrinsics are lowered into the nodes. Try to directly simplify them
so they are matched before the bit assert operations can be optimized
out.

llvm-svn: 369994
parent e6561e00
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment