[AArch64][SVE] Add addressing mode for contiguous loads & stores

Summary:
This patch adds the register + register addressing mode for
SVE contiguous load and store intrinsics (LD1 & ST1)

Reviewers: sdesmalen, fpetrogalli, efriedma, rengolin

Reviewed By: fpetrogalli

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78509