Minor fixups to LLDB AArch64 register infos macros for SVE register infos

Summary:
This patch adds some cosmetic changes to LLDB AArch64 register infos macros in order to use them in SVE register infos struct in follow up patches.
This patch initially added invalidate lists to register infos struct but that is no longer needed and problem disappeared after updating qemu testing environment.

old headline comments for reference:
AArch64 reigster X and V registers are primary GPR and vector registers respectively. If these registers are modified their corresponding children w regs or s/d regs should be invalidated. Specially when a register write fails it is important that failure gets reflected to all the registers which draw their value from a particular value register.

Reviewers: labath, rengolin

Reviewed By: labath

Subscribers: tschuett, kristof.beyls, danielkiss, lldb-commits

Differential Revision: https://reviews.llvm.org/D77045