Make `shouldExpandLogicAtomicRMWInIR` able to match both operands.

Previous logic was buggy and erroneously asserted that I->operand(0) must
be the RMW instruction. This change fixes that and makes it so that the
RMW instruction can be used in operand 0 or 1.

Also update the tests to explicitly test RMW as operand 0/1 (no change
to codegen).

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D142166