[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.

Added support of TTMP quads.
Reworked M0 exclusion machinery for SMRD and similar instructions
to enable usage of TTMP registers in those instructions as destinations.
Tests added.

Differential Revision: http://reviews.llvm.org/D19342

llvm-svn: 267733