[AArch64][CodeGen] Allow vectors larger than hardware support to use SVE's...

[AArch64][CodeGen] Allow vectors larger than hardware support to use SVE's load zero/sign-extend for fixed vectors.

Prefer to fold LOAD + SIGN/ZEROEXTEND to SVE load and sign extend instructions
for fixed-length-vectors even if a type is not representable on a hardware.

Differential Revision: https://reviews.llvm.org/D147533