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Unverified Commit 4793c2c3 authored by Yingwei Zheng's avatar Yingwei Zheng Committed by GitHub
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[DAGCombiner][RISCV] Prefer to sext i32 non-negative values (#65984)

By default, `DAGCombiner` folds `sext x` to `zext x` when `x` is
non-negative. It will generate redundant `zext` inst seq on riscv64
(typically `slli (srli x, 32), 32`).
godbolt: https://godbolt.org/z/osf6adP1o
This patch applies the transform iff `zext` is **cheaper** than `sext`.
parent ea42c4ac
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