[RISCV] Fix some errors in the vector part of the scheduler model for SiFive7.

-FP compare latency was too high.
-Compare instructions need to increase latency to assume no chaining
to later instructions.

vmv.x.s, vmv.s.x, vfmv.f.s, and vfmv.s.f aren't 8 cycles. From the
the perspective of the vector pipeline they are only 4 cycles. Though
vector to scalar has a much higher latency from the perspective
of the scalar pipeline. Will need to adjust in the future.

Reviewed By: michaelmaitland

Differential Revision: https://reviews.llvm.org/D151136