Restrict vext.x.v, vmv.s.x, vfmv.f.s and vfmv.s.f instructions to LMUL=1

- It fixes #13.
- Those instructions ignore LMUL and register groups.
- Add missing gvl operator to int.epi.vfmv.f.s intrinsic.
- Make sure that int.epi.vext.x.v intrinsic is expanded into the
  vsetvli+pseudo combo. Even if vext.x.v instruction ignores the value
  of VL, we need to set vtype so that the SEW matches the intrinsic
  type.