[X86] Add test cases to show missed opportunities to remove AND mask from...

[X86] Add test cases to show missed opportunities to remove AND mask from BTC/BTS/BTR instructions when LHS of AND has known zeros.

We can currently remove the mask if the immediate has all ones in the LSBs, but if the LHS of the AND is known zero, then the immediate might have had bits removed.

A similar issue also occurs with shifts and rotates. I'm preparing a common fix for all of them.

llvm-svn: 354520