[TableGen][AsmMatcherEmitter] Fix tied-constraint checking for InstAliases

Summary:
This is a bit of a reimplementation the work done in
https://reviews.llvm.org/D41446, since that patch only really works for
tied operands of instructions, not aliases.

Instead of checking the constraints based on the matched instruction's opcode,
this patch uses the match-info's convert function to check the operand
constraints for that specific instruction/alias.
This is based on the matched operands for the instruction, not the
resulting opcode of the MCInst.

This patch adds the following enum/table to the *GenAsmMatcher.inc file:
  enum {
    Tie0_1_1,
    Tie0_1_2,
    Tie0_1_5,
    ...
  };

  const char TiedAsmOperandTable[][3] = {
    /* Tie0_1_1 */ { 0, 1, 1 },
    /* Tie0_1_2 */ { 0, 1, 2 },
    /* Tie0_1_5 */ { 0, 1, 5 },
    ...
  };

And it is referenced directly in the ConversionTable, like this:
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][13] = {
  ...
  { CVT_95_addRegOperands, 1,
    CVT_95_addRegOperands, 2,
    CVT_Tied, Tie0_1_5,
    CVT_95_addRegOperands, 6, CVT_Done },
  ...


The Tie0_1_5 (and corresponding table) encodes that:
* Result operand 0 is the operand to copy (which is e.g. done when
  building up the operands to the MCInst in convertToMCInst())
* Asm operands 1 and 5 should be the same operands (which is checked
  in checkAsmTiedOperandConstraints()).

Reviewers: olista01, rengolin, fhahn, craig.topper, echristo, apazos, dsanders

Reviewed By: olista01

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42293

llvm-svn: 324196