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Commit 5ced5961 authored by Abderrazek Zaafrani's avatar Abderrazek Zaafrani
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[AArch64] Improve FP16 instruction selection for vector round and vector... 

[AArch64] Improve FP16 instruction selection for vector round and vector conver from half instructions
https://reviews.llvm.org/D58855

llvm-svn: 355545
parent e1012e1e
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