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Commit 63f21f4c authored by Stanislav Mekhanoshin's avatar Stanislav Mekhanoshin
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[AMDGPU] Handle LDS DMA and LDS_DIRECT hazards 

There shall be 1 wait state between M0 write and LDS DMA/LDS_DIRECT use.

Differential Revision: https://reviews.llvm.org/D124550
parent bc78c099
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